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JOP of RAM VHDL source code, classic classics, difficult to find a good price.

于 2022-10-01 发布文件大小:3.98 kB

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JOP的RAM VHDL源码，经典的经典，不易找到的好东东，-JOP of RAM VHDL source code, classic classics, difficult to find a good price.

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Writing Testbenches using System Verilog
Material to learn how to use system verilog and how to write testbenches for verification.

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lut_multiplier
使用verliog设计实现LUT查找表乘法器，通过modelsim仿真验证通过(Designed and implemented using the LUT lookup table verliog multipliers, through simulation by modelsim)

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bitcount
it will count the bit

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StepMotor_CurrentLoop
说明：实现二项混合式步进电机的驱动，和步进电机的细分程序。(The driving of binomial hybrid stepper motor and the subdivision program of stepper motor are realized.)

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rams
combinatorial modules

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EDA very important small procedures to ensure that key reliability and prevent j...
EDA中很重要的小程序，保证按键可靠性，防止抖动误差信号产生，外部信号输入时必用此消抖函数-EDA very important small procedures to ensure that key reliability and prevent jitter error signal generated, the external input signal must use this function Consumers shiver

2022-02-13 11:15:40下载

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ADc
与单片机相比，用CPLD/FPGA器件更适合于直接对高速AD采样控制。本实验接口器件为ADC0809，根据ADC0809的工作时序使用CPLD产生该控制信号，CPLD启动AD转换后，得到的数据送至单片机并在PC机及数码管上显示AD转换结果。(Compared with the microcontroller, CPLD/FPGA devices more suitable for direct sampling control of high-speed AD. The interface of the experimental device for the ADC0809 ADC0809 Timing CPLD is used to generate the control signal, the CPLD to start the AD conversion, the data sent to the microcontroller and the AD conversion result on the PC and digital tube display)

2021-03-29 11:19:10下载

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verilog实现的“BCD/七段译码器”。
verilog实现的“BCD/七段译码器”。-verilog implementation " BCD/Seven-Segment Decoder."

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tb_modular
说明： Matlab to hdl code for Least_square testbench

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7941952NCO_sin
NCO 代码设计使用VHDL语言 (nco)

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JOP of RAM VHDL source code, classic classics, difficult to find a good price.

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