登录
首页 » VHDL » JOP of RAM VHDL source code, classic classics, difficult to find a good price.

JOP of RAM VHDL source code, classic classics, difficult to find a good price.

于 2022-10-01 发布 文件大小:3.98 kB
0 94
下载积分: 2 下载次数: 1

代码说明:

JOP的RAM VHDL源码,经典的经典,不易找到的好东东,-JOP of RAM VHDL source code, classic classics, difficult to find a good price.

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • Writing Testbenches using System Verilog
    Material to learn how to use system verilog and how to write testbenches for verification.
    2018-02-09 17:24:25下载
    积分:1
  • lut_multiplier
    使用verliog设计实现LUT查找表乘法器,通过modelsim仿真验证通过(Designed and implemented using the LUT lookup table verliog multipliers, through simulation by modelsim)
    2021-04-09 10:18:59下载
    积分:1
  • bitcount
    it will count the bit
    2010-03-13 23:53:26下载
    积分:1
  • StepMotor_CurrentLoop
    说明:  实现二项混合式步进电机的驱动,和步进电机的细分程序。(The driving of binomial hybrid stepper motor and the subdivision program of stepper motor are realized.)
    2020-06-21 02:20:01下载
    积分:1
  • rams
    combinatorial modules
    2019-04-13 19:41:21下载
    积分:1
  • EDA very important small procedures to ensure that key reliability and prevent j...
    EDA中很重要的小程序,保证按键可靠性,防止抖动误差信号产生,外部信号输入时必用此消抖函数-EDA very important small procedures to ensure that key reliability and prevent jitter error signal generated, the external input signal must use this function Consumers shiver
    2022-02-13 11:15:40下载
    积分:1
  • ADc
    与单片机相比,用CPLD/FPGA器件更适合于直接对高速AD采样控制。本实验接口器件为ADC0809,根据ADC0809的工作时序使用CPLD产生该控制信号,CPLD启动AD转换后,得到的数据送至单片机并在PC机及数码管上显示AD转换结果。(Compared with the microcontroller, CPLD/FPGA devices more suitable for direct sampling control of high-speed AD. The interface of the experimental device for the ADC0809 ADC0809 Timing CPLD is used to generate the control signal, the CPLD to start the AD conversion, the data sent to the microcontroller and the AD conversion result on the PC and digital tube display)
    2021-03-29 11:19:10下载
    积分:1
  • verilog实现的“BCD/七段译码器”。
    verilog实现的“BCD/七段译码器”。-verilog implementation " BCD/Seven-Segment Decoder."
    2022-12-23 05:15:02下载
    积分:1
  • tb_modular
    说明:  Matlab to hdl code for Least_square testbench
    2020-06-17 12:20:02下载
    积分:1
  • 7941952NCO_sin
    NCO 代码设计 使用VHDL语言 (nco)
    2009-05-23 16:39:37下载
    积分:1
  • 696518资源总数
  • 105895会员总数
  • 18今日下载