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用于实现sin，cos三角函数计数的VHDL程序代码
用于实现sin，cos三角函数计数的VHDL程序代码-towards sin, cos trigonometry count VHDL code
- 2022-01-25 23:34:00下载
- 积分：1
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9850sin_function
ad9850函数发生器 MSP430单片机驱动程序 扫频 DDS(AD9850 DDS)
- 2013-08-27 15:13:29下载
- 积分：1
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adc
采用quartus的数模转换模块，RTL电路图(DAC module, RTL circuit diagram)
- 2018-08-27 11:09:01下载
- 积分：1
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Mult_Frequency
Based on the verilog such as frequency meter accuracy, except for measuring frequency can also measure pulse width of empty measure than 32 counts of data through the simulation SPI serial output to SCM processing and display
- 2011-07-27 10:26:29下载
- 积分：1
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tr_wave
FPGA编写的三角波发生器，可以产生100HZ～500KHZ以上的三角波，波形稳定(FPGA prepared triangular wave generator, can produce more than 100HZ ~ 500KHZ triangle wave, waveform stability)
- 2007-08-25 03:15:38下载
- 积分：1
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低功率的可逆逻辑乘8
本文提出了一种新颖的可逆乘法器。可逆逻辑可以发挥重要作用
- 2023-01-29 11:35:03下载
- 积分：1
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第七次课--视频图像DCT处理及水印嵌入_2
说明： 熟悉IIC协议总线协议，采用IIC总线对图像采集传感器寄存器进行配置，并转换为RGB565格式。
利用异步FIFO完成从摄像头输出端到SDRAM 和SDRAM 到VGA 接口各跨时钟域信号的传输和处理。
利用 SDRAM 接口模块的设计，实现了刷新、读写等操作；为提高SDRAM 的读写带宽，均采用突发连续读写数据方式；并采用乒乓操作实现 CMOS 摄像头与VGA的帧率匹配。
利用双线性插值方法实现对图像640×480到1024×768的放大操作。
完成VGA显示接口设计。(Familiar with IIC protocol bus protocol, IIC bus is used to configure the register of image acquisition sensor and convert it into RGB565 format.
Asynchronous FIFO is used to transmit and process signals across clock domain from camera output to SDRAM and SDRAM to VGA interface.
With the design of SDRAM interface module, refresh, read and write operations are realized. In order to improve the read and write bandwidth of SDRAM, burst continuous read and write data mode is adopted, and table tennis operation is used to achieve frame rate matching between CMOS camera and VGA.
The bilinear interpolation method is used to enlarge the image from 640*480 to 1024*768.
Complete the VGA display interface design.)
- 2020-06-25 04:00:02下载
- 积分：1
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VHDL_COUNTING 时间使用按钮 (Đếm giờ phút giây sử dụng nút nhấn)
VHDL_COUNTING 时间使用按钮 (Đếm giờ phút giây sử dụng nút nhấn)
- 2022-01-27 10:40:51下载
- 积分：1
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freeDev数字应用开发板中的七段数码管的IP核的verilog实现
freeDev数字应用开发板中的七段数码管的IP核的verilog实现-freeDev digital application development boards in the seven-segment digital tube of the IP core implementation of the verilog
- 2022-01-31 19:57:07下载
- 积分：1
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ccd
自己写的一个tcd1209d的时序驱动代码，是用verilog语言编写的，可以借鉴(Of write a tcd1209d of timing-driven code, Verilog language, can learn from)
- 2021-04-08 09:39:00下载
- 积分：1
