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xilinx CTC IPcore(encoder 和 decoder）的标准测试，未经信道加噪
xilinx CTC IPcore(encoder 和 decoder）的标准测试，未经信道加噪-the standard test of xilinx CTC IPcore (encoder and decoder) , without the channel with noise
- 2022-04-25 17:11:32下载
- 积分：1
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bundle_test5
说明： 一个具备bp协议典型功能的数据传输系统（超时重传机制以及托管传输）包含五个节点(A data transmission system with typical functions of BP protocol (Overtime retransmission mechanism and managed transmission) consists of five nodes)
- 2019-12-02 19:06:44下载
- 积分：1
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这是我用vhdl语言，在fpga内部做了一个双口ram的程序。我的邮箱：wleechina@163.com...
这是我用vhdl语言，在fpga内部做了一个双口ram的程序。我的邮箱：wleechina@163.com-This is the language I used vhdl in fpga done an internal dual-port ram procedures. My mail : wleechina@163.com
- 2022-05-06 16:15:30下载
- 积分：1
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sinwave
使用verilog hdl语言编程正弦波信号，能仿真出结果(Can use verilog HDL language programming sine wave signal, the simulation results
)
- 2013-09-18 15:27:27下载
- 积分：1
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hamid
very nice program that i ensure anyone can use easily and will be efficient for hard project of elevator
- 2009-07-26 13:27:38下载
- 积分：1
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流水线乘法器的VHDL实现，希望对你会有用！
流水线乘法器的VHDL实现，希望对你会有用！-Pipelined multiplier in VHDL implementation, you will want to use!
- 2023-04-03 22:35:03下载
- 积分：1
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VHDL
带有异步清零、异步置位功能的边沿JK触发器(With asynchronous reset, asynchronous setting function of edge JK flip-flop)
- 2020-06-30 03:00:02下载
- 积分：1
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VHDL_biss
FPGA中针对Biss通讯协议解码VHDL语言源码(FPGA communication protocols against BiSS source decoder VHDL language)
- 2021-03-15 19:19:22下载
- 积分：1
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VHDL实现 8051 CPU核 Oregano Systems 8
VHDL实现 8051 CPU核 Oregano Systems 8-bit Microcontroller IP-Core-VHDL 8051 CPU nuclear Oregano Systems 8-bit Mic rocontroller IP-Core
- 2022-01-21 00:52:30下载
- 积分：1
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I2C_read
说明： I2C读程序，通过状态机描叙,仿真达到要求(I2C Reading, depicts through the state machine, called Simulation)
- 2006-04-07 15:51:19下载
- 积分：1
