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project_1
简单的一个Verilog小程序，适合刚接触的人群(A simple Verilog small program, suitable for people just contact)
- 2020-06-16 22:20:01下载
- 积分：1
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pdf
说明： 一种基于FPGA的调频连续波方位向多通道
FMCW SAR的实时成像信号处理方法及FPGA，包
括：步骤一、计算重构矩阵；步骤二、重构方位向
多通道数据，包括：步骤2 .1、对各个通道的回波
数据沿方位向分别间隔补零，并进行方位向傅里
叶变换；步骤2 .2、将方位向傅里叶变换之后各个
通道方位向相同位置的点组合为一个向量并与
重构矩阵相乘，得到重构完成的方位向数据；(An azimuth multichannel FMCW based on FPGA
FMCW SAR real-time imaging signal processing method and FPGA, package
Including: Step 1: calculate the reconstruction matrix; step 2: reconstruct the orientation
Multichannel data, including: step 2.1, echo of each channel
The data is compensated with zero along the azimuth direction respectively, and the azimuth Fourier is carried out
Step 2.2, after the azimuth Fourier transform
The points of the same position in the channel azimuth are combined into a vector and are connected withThe reconstruction matrix is multiplied to get the reconstructed azimuth data
Step 2.3. Repeat step 2.3 for the data of different distance gates)
- 2020-02-07 19:47:41下载
- 积分：1
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CPLD_DEMO_OK
可以给VHDL初学者看的实例，全部经过验证(VHDL beginners can see examples of all the proven)
- 2011-01-12 21:09:45下载
- 积分：1
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weifenqi
微分器：利用数字锁相环进行位同步信号提取的关键模块(Differentiator: the use of digital phase-locked loop for bit synchronous signal extraction of key modules)
- 2020-12-01 10:39:28下载
- 积分：1
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cyclone3_handbook-datasheet
cyclone3_handbook-datasheet
- 2018-10-26 21:28:06下载
- 积分：1
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是使用VHDL语言编写的基于FPGA的uart的源代码！
是使用VHDL语言编写的基于FPGA的uart的源代码！-VHDL language is to use FPGA-based uart source code!
- 2022-07-10 13:34:40下载
- 积分：1
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vhdl5
program for half subtractor.
- 2009-10-02 16:10:13下载
- 积分：1
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用VHDL写的源代码程序，包涵三人表决器，七人表决器，全加器以及模24，模60的计数器，都是单文件的，由于程序小又多，所以集中在一起，供新学习VHDL语言的朋友...
用VHDL写的源代码程序，包涵三人表决器，七人表决器，全加器以及模24，模60的计数器，都是单文件的，由于程序小又多，所以集中在一起，供新学习VHDL语言的朋友们参考。-With VHDL source code written procedures, includes three of the voting machine, vote on seven people, and full adder, as well as modulus 24, modulus 60 counters, are single-file, as many small procedures, so together for the new Learning VHDL Language Reference friends.
- 2022-02-02 08:32:12下载
- 积分：1
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decodeLogDomainSimple
When the initial input falls between the Switch off point and Switch on point values, the initial output is the value when the relay is off.
- 2017-01-29 18:04:53下载
- 积分：1
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medianfilter
图像滤波中的中值滤波，有效滤除椒盐噪声，使用verilog语言编写(Image filtering in the median filter, effectively filter out salt and pepper noise, using verilog language)
- 2011-10-13 17:08:48下载
- 积分：1
