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EDA常用计数函数VHDL程序设计，减法计数器：可预置数：
EDA常用计数函数VHDL程序设计，减法计数器：可预置数：-common counting function EDA VHDL programming, subtraction counter : Preset :
- 2022-03-25 01:33:15下载
- 积分：1
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PIP
基于FPGA的画中画处理PDF技术文档，采用SD卡里图片读出来做为底图，然后再图上叠加另外一个图片或者视频(Based on the FPGA picture in picture processing PDF technical documentation
)
- 2014-07-10 17:56:04下载
- 积分：1
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基于FPGA的OFDM信号传输系统VHDL源码
基于FPGA(Field-Programmable Gate Array)的OFDM(Orthogonal Frequency Division Multiplexing)信号传输系统VHDL源码
use IEEE.std_logic_unsigned.all;
package outconverter is
constant stage : natural := 3;
constant FFTDELAY:integer:=13+2*STAGE;
constant FACTORDELAY:integer:=6;
constant OUTDELAY:integer:=9;
function counter2addr(
counter : std_logic_vector;
mask1:std_logic_vector;
mask2:std_logic_vector
) return std_logic_vector;
function outcounter2addr(counter : std_logic_vector) return std_logic_vector;
end outconverter;
package body outconverter is
function counter2addr(
counter : std_logic_vector;
mask1:std_logic_vector;
mask2:std_logic_vector
) return std_logic_vector is
variable result :std_logic_vector(counter"range);
begin
for n in mask1"range loop
if mask1(n)="1" then
result( 2*n+1 downto 2*n ):=counter( 1 downto 0 );
elsif mask2(n)="1" and n/=STAGE-1
- 2022-02-13 14:58:13下载
- 积分：1
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UART_RX_
fpga串口的发送程序基于verilog语言拿走不用谢。(The sending program of FPGA serial port is based on Verilog language.)
- 2020-06-18 04:00:01下载
- 积分：1
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Cordic_matlab
实现自然对数运算的cordic算法的matlab浮点仿真，以及针对FPGA硬件平台的定点仿真测试(Achieve natural logarithm of cordic algorithm matlab floating point emulation, and FPGA hardware platform for fixed-point simulation testing)
- 2013-11-01 15:10:09下载
- 积分：1
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In Altera
在Altera的FPGA开发板上运行第一个FPGA程序，以后我还会陆续发布这方面的代码-In Altera
- 2022-03-11 01:12:51下载
- 积分：1
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vhdl
vhdl code for internet interface
- 2014-12-04 04:58:04下载
- 积分：1
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595_8led
74hc595 driver 8 led
- 2013-03-28 21:10:33下载
- 积分：1
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本程序是用VHDL语言实现电子密码锁功能,整个系统分为三大模块,一为控制模块,二为键盘显示模块,三为处理模块...
本程序是用VHDL语言实现电子密码锁功能,整个系统分为三大模块,一为控制模块,二为键盘显示模块,三为处理模块-This procedure is a VHDL language electronic code lock function, the entire system is divided into three modules, one for the control module, two for the keyboard display module, three modules for the treatment
- 2022-05-08 19:29:46下载
- 积分：1
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Vhdl实现的鼠标协议历程，代码可读性高，适合作为案例参考。
Vhdl实现的鼠标协议历程，代码可读性高，适合作为案例参考。-VHDL realize the course of the mouse protocol, code readable, suitable as a reference case.
- 2023-05-02 16:50:03下载
- 积分：1
