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shi01
FPGA上机文件一所以在FPGA中采用同 步设计非常重要 MAX+PLUS II可以计算出数据传输需要(fpga Several of the largest chip operating frequency I would be grateful if the output value of counter FFFFC- FE0FF simulation waveform between the print out (only EPF10K70RC240-4 chips, the maximum allowable Clock frequency)
- 2017-10-24 16:41:14下载
- 积分：1
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LMS算法FPGA仿真
自适应滤波器算法LMS ，的FPGA实现，采用VERILOG实现。(LMS, an adaptive filter algorithm, is implemented on FPGA and VERILOG.)
- 2020-06-24 01:00:02下载
- 积分：1
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基于fpga的正弦波发生器设计，有一定的参考价值，写的比较详细...
基于fpga的正弦波发生器设计，有一定的参考价值，写的比较详细-The sine wave generator based on FPGA design, have a certain reference value, a more detailed written
- 2022-12-22 09:40:03下载
- 积分：1
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Pipeline-2
Pipeline processor verilog components
- 2012-12-21 17:53:18下载
- 积分：1
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Divider-vhdl
This is a divider, which is depicted as well.
It is a programming language Vhdl.
- 2013-09-29 18:28:11下载
- 积分：1
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一百多个例子很好的verilog 学习资料，大家可以多多参考，适合初学者学习...
一百多个例子很好的verilog 学习资料，大家可以多多参考，适合初学者学习-More than 100 examples of good learning materials Verilog, you can a lot of reference, suitable for beginners to learn
- 2022-03-10 00:01:48下载
- 积分：1
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verilogdct
dct实现verilog hdl的数字图像处理，源代码(dct achieve verilog hdl digital image processing, source code)
- 2020-12-02 17:49:26下载
- 积分：1
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FPGA开发全攻略
FPGA设计攻略及流程，包含时序收敛和引脚约束(FPGA design strategy and process, including time series convergence and pin constraints)
- 2017-12-12 16:30:52下载
- 积分：1
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FFT
FFT with FIR created by students in univercity
- 2015-06-22 14:57:30下载
- 积分：1
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EDA VHDL modules commonly used procedure, the time
EDA中常用模块VHDL程序，不同时基的计数器由同一个外部是中输入时必备的分频函数。分频器FENPIN1/2/3(50分频=1HZ，25分频=2HZ，10分频=5HZ。稍微改变程序即可实现)-EDA VHDL modules commonly used procedure, the time- with a counter by the external input is required when the sub-frequency functions. Frequency Divider FENPIN1/2/3 (50 1HZ frequency = 25 = 2HZ-frequency, frequency = 10 points Stripper. A slight change in procedure can be realized)
- 2022-07-02 21:52:46下载
- 积分：1
