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67_ellipf
vhdl very good debug release vhdl very good debug release
- 2006-10-22 18:39:48下载
- 积分：1
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test
简单的232-485通信程序！主要是串口跟485之间的通信，起到发送接收然后再另一边显示的功能！(Simple 232-485 communication program!)
- 2012-09-26 19:54:40下载
- 积分：1
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alarm
闹钟设计，VHDL，源代码。闹钟设计，VHDL，源代码。(Alarm clock design, VHDL, the source code.)
- 2011-05-23 18:30:29下载
- 积分：1
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基于fpga的实时视频采集与显示
高速化 小型化
基于fpga的实时视频采集与显示
高速化 小型化-fpga
- 2022-01-30 23:55:32下载
- 积分：1
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pprobar
ES A PRACRICA 2 DEL LABORATORIO DE DIGITAL
- 2013-12-09 04:26:42下载
- 积分：1
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Single-CPU
说明： 简单的单周期CPU设计，实现的指令有：算术运算指令、逻辑运算指令、移位指令、比较指令、存储器读/写指令、分支指令、跳转指令、停机指令。(Simple single-cycle CPU design,The instructions implemented are as follows:Arithmetic operation instruction, logical operation instruction, shift instruction, comparison instruction, memory read/write instruction, branch instruction, jump instruction, stop instruction.)
- 2020-06-16 12:28:32下载
- 积分：1
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5. For the key to enter a password lock, assuming that reset after the seven lam...
5对于进入密码锁的钥匙，假设复位后七节灯显示为" 0"，而使用sw1、sw2两个，则sw2-> sw1-> sw1-> sw2，则表示解锁右侧将导致七节灯显示为" 8"
- 2023-06-12 23:35:07下载
- 积分：1
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VHDL的循环冗余校验发生器和接收器
VHDL cyclic redundancy check generator und receiver
- 2022-01-23 11:24:26下载
- 积分：1
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vhdl
说明： 学习VHDL可以用得上，有很多实例，可以对照着自己写一些东西(VHDL can be useful to learn, there are many examples, can be done to write something)
- 2008-10-31 20:59:04下载
- 积分：1
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DDS_Power
FPGA上的VERILOG语言编程。通过查找表实现直接数字频率合成。在主控部分通过键盘选择正弦波，方波，三角波，斜波，以及四种波形的任意两种的叠加，以及四种波形的叠加；通过控制频率控制字C的大小，以控制输出波形频率，实现1Hz的微调；通过地址变换实现波形相位256级可调；通过DAC0832使波形幅值256级可调；通过FPGA内部RAM实现波形存储回放；并实现了每秒100HZ扫频。(FPGA on the verilog language programming. Lookup table through direct digital frequency synthesis. In part through the control of the keyboard to choose sine, square, triangle wave, sloping wave, and four arbitrary waveform two superposed and the stack of four waveform; by controlling the frequency control word on the size, in order to control the output waveform frequency, 1 Hz to achieve the fine-tuning; Address transform through waveform phase adjustable 256; DAC0832 so through waveform amplitude adjustable 256; FPGA through internal RAM to the waveform storage intervals; and achieve a 100 per second sweep 9999.)
- 2007-04-17 23:43:32下载
- 积分：1
