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2018全国大学生FPGA大赛封闭测试上机题
说明: 2018全国大学生FPGA创新设计大赛南京总决赛封闭测试题目,以及自己编写的verilog和testbench,欢迎学习借鉴(The closed test topic of the 2018 National Undergraduate FPGA innovation design competition Nanjing finals, as well as Verilog and testbench compiled by ourselves, are welcome to learn)
- 2020-11-23 22:39:33下载
- 积分:1
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用VHDL编写的RS232串口的通信程序
用VHDL编写的RS232串口的通信程序-Written with the VHDL serial RS232 communication program
- 2022-05-06 01:41:31下载
- 积分:1
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内嵌BRAM设计LIFO堆栈
具有先进后出的堆栈功能。此LIFO堆栈具有两个按键(write, read),按下write键后,开始输入数据data0-data3;按下read键后,7段数码管开始倒序显示data3-data0(十进制)。
高级要求(可选): 按下write键,VGA显示“Write”字样,并同时显示输入数据;按下read键,VGA显示“Read”字样,并同时显示输出数据。
- 2022-04-29 13:49:12下载
- 积分:1
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VHDLcoding
本文件时VHDL的各种编写规范,有助于开发者在平时养成好的编码习惯(This document, the various write VHDL specification, helps developers to develop good coding habits in peacetime)
- 2009-11-20 11:44:58下载
- 积分:1
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本实施multilplier在vhdl.this源代码是有用的电脑学习…
this implemented multilplier in vhdl.this source code is useful for computer student and hardware engineering.-this is implemented multilplier in vhdl.this source code is useful for computer student and hardware engineering.
- 2022-01-31 00:27:28下载
- 积分:1
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加扰器解扰器设计
加扰器解扰器设计,组合逻辑电路可以选用下述不同的逻辑类型来实现:互补CMOS结构、有比电路、差 分共源-共栅电压开关逻辑(DCVSL),传输门逻辑、互补传输晶体管逻辑(CPL)或动态电 路结构,也可以是以上不同类型结构的混合。(Scrambler/ descrambler design)
- 2018-08-29 10:52:46下载
- 积分:1
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根据音乐发生的机理,将复杂可编程逻辑器件作为发生音乐的核心器件,用高速集成电路硬件描述语言编程描述发生的音乐乐谱,配合周边硬件电路,由电声转换发声器接收信号,从...
根据音乐发生的机理,将复杂可编程逻辑器件作为发生音乐的核心器件,用高速集成电路硬件描述语言编程描述发生的音乐乐谱,配合周边硬件电路,由电声转换发声器接收信号,从而发出音乐声,实验表明,采用该方法设计的音乐发生器成本低、修改方便-Music took place in accordance with the mechanism of complex programmable logic device, as occurred in the core of music devices, with high-speed integrated circuit hardware description language to describe the occurrence of music notation, with the peripheral hardware circuits, electro-acoustic conversion by the audible signal device to receive signals, which issued music, experiments show that this method of music generator design and low cost, easy to amend
- 2023-06-27 23:25:04下载
- 积分:1
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FPGA verilog代码
说明: 数电实验FPGA verilog代码,包括秒表、全加器、半加器等。(FPGA Verilog code for digital experiment)
- 2020-04-29 11:16:05下载
- 积分:1
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CJ2
关键词:清华大学计算机系 计算机组成原理大实验 多周期cpu工程源码,内含中断,串口,以及31个指令的实现,读写内存,控制器,ALU,寄存器,分频等模块,小作业什么的可以直接从里面摘抄,为学弟学妹造福(Keywords: Department of Computer Science Computer Composition Principle experimental multi-cycle the cpu Engineering source for the benefit of mentees)
- 2020-12-29 10:09:01下载
- 积分:1
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sonic
基于FPGA的超声波测距,通过数码管显示距离(FPGA-based ultrasonic distance)
- 2015-04-27 15:41:19下载
- 积分:1