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en.SPI_EEPROM_Verilog_models_V10
spi接口的eeprom模型,型号为st公司m65pxx(The eeprom model of spi interface is st company m65pxx)
- 2021-01-19 14:28:44下载
- 积分:1
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ofdm
这是OFDM调制matlab的程序,中间详细描述了调制的过程,希望对大家有用。(This is the OFDM modulation matlab procedures, a detailed description of the intermediate modulation process, I hope useful.)
- 2013-09-26 16:20:42下载
- 积分:1
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soft for changing Verilog code to c++ code ,c code
将Verilog代码转换成C++代码的软件,C源代码。-soft for changing Verilog code to c++ code ,c code
- 2022-01-24 14:30:24下载
- 积分:1
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MUX
说明: 用CASE实现4选1数据选择器 很实用 运用VERILOG(Using CASE to achieve 4 election 1 Data Selector practical use Verilog)
- 2008-09-11 11:37:35下载
- 积分:1
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sobel
在FPGA中,采用verilog HDL语言实现图像处理算法sobel,仿真实验通过(In the FPGA using verilog HDL language image processing algorithms sobel, simulation experiment)
- 2021-01-15 20:58:46下载
- 积分:1
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SAR-ADC
Complete Successive approximation Analog to digital converter along with the source code
- 2013-04-21 23:42:03下载
- 积分:1
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GW48系统电子琴:可控制8个音节,4种音调 readme中带使用说明
GW48系统电子琴:可控制8个音节,4种音调 readme中带使用说明-GW48 system : control eight syllables, four species of taking the pitch readme use
- 2022-05-21 12:22:34下载
- 积分:1
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gold
基于vhdl语言的15位gold序列的设计的开端一部分程序(Vhdl language based on sequences of the 15 gold as part of the beginning of the design process)
- 2011-05-16 21:48:38下载
- 积分:1
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一个用vhdl硬件描述语言实现的一个比较简单的除法器
一个用vhdl硬件描述语言实现的一个比较简单的除法器-an divider using vhdl
- 2022-05-15 11:56:12下载
- 积分:1
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gcounter1
数字钟vhdl实现,在线测试无误,具有闹钟,对表功能(Digital clock vhdl implementation, online testing is correct, with alarm, the table function)
- 2013-10-19 22:06:16下载
- 积分:1