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VHDL Storage/counter design
vhdl寄存/计数器设计-VHDL Storage/counter design
- 2022-01-26 02:37:06下载
- 积分:1
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RD1006
RD1006--I2C与存储器的IP
代码及说明文档,lattice提供,I2C Controller for Serial EEPROMs 源代码可用,并且包含tb文件-RD1006-- I2C and memory IP code and documentation. Lattice offer I2C Controller for Serial EEPROMs source code available, and document contains tb-
- 2023-07-29 23:55:03下载
- 积分:1
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一个完整的设计DE2_project,希望对大家有所帮助,谢谢ok
一个完整的设计DE2_project,希望对大家有所帮助,谢谢ok-A complete design DE2_project, everyone would like to be helpful, thank you ok
- 2022-04-18 05:42:24下载
- 积分:1
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GAL
有关gal器件的编程入门,以及常见逻辑门、计数器VHDL程序(For gal device programming entry, as well as common logic gates, counters VHDL program)
- 2013-07-09 22:50:01下载
- 积分:1
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用verilog语言实现的霍夫曼压缩编码算法
说明: 一种用verilog语言实现的霍夫曼压缩编码算法(Huffman compression implemented by Verilog)
- 2019-11-18 18:29:45下载
- 积分:1
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Xilinx的FPGA开发DEMO例程,功能相对来说比较全面,适合新手参考。...
Xilinx的FPGA开发DEMO例程,功能相对来说比较全面,适合新手参考。-Xilinx FPGA development DEMO routines, function relatively comprehensive reference suitable for novice.
- 2022-02-21 21:55:12下载
- 积分:1
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pingpangqiu
基于basys2的简单的乒乓球小游戏,通过ise13.4开发,使用语言VHDL,能够通过VGA在显示屏显示,能够实现双人对打,有计分功能。(Simple table tennis game, based on basys2 through ise13.4 development, using VHDL language, can through the VGA display shows, can achieve a double play, scoring function.)
- 2014-07-04 01:42:00下载
- 积分:1
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Advanced-FPGA-Design
Advanced FPGA Design - Architecture, Implementation, and Optimization(Advanced FPGA Design- Architecture, Implementation, and Optimization)
- 2015-04-13 16:00:33下载
- 积分:1
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code
adder 18b trong chuong trinh verilog
- 2017-11-26 14:34:56下载
- 积分:1
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看门狗定时器
使用IEEE.STD_LOGIC_1164.ALL; - 取消对以下库声明,如果用符号或无符号值using--算术功能 - 使用IEEE.NUMERIC_STD.ALL; - 取消对以下库声明如果instantiating--任何Xilinx基元在这代码.--库UNISIM; - 使用UNISIM.VComponents.all;实体看门狗端口(SYSRST:在STD_LOGIC; SYSCLK:在STD_LOGIC; WR:在STD_LOGIC; DATAIN:在STD_LOGIC_VECTOR(7 DOWNTO0); RESETOUT:出STD_LOGIC; debugStates:出STD_LOGIC_VECTOR(1 DOWNTO0); debugDivider:出STD_LOGIC; debugFlag:出STD_LOGIC);年底看门狗,看门狗建筑行为issignal timeoutSelect:STD_LOGIC_VECTOR(1 DOWNTO0);信号timerRestart:STD_LOGIC;信号timerEnable:STD_LOGIC;组件wdtcntl端口(调试:出STD_LOGIC_VECTOR(1 DOWNTO0);系统时钟:在STD_LOGIC; SYSRST:在STD_LOGIC; WR:在STD_LOGIC; DATAIN:在STD_LOGIC_VECTOR(7 DOWNTO0);重新启动:从STD_LOGIC; timerEnb:出STD_LOGIC; timerSel:出STD_LOGIC_VECTOR(1 DOWNTO0));最终组件;组件wdt_timer端口(dbDivider:出STD_LOGIC; DBFLAG:出STD_LOGIC; SYSRST:在STD_LOGIC; SYSCLK:在STD_LOGIC;启用:在STD_LOGIC;重启:在STD_LOGIC; RESETOUT:出STD_LOGIC; timeoutSel:在STD_LOGIC_VECTOR(1 DOWNTO0 ));结束部分; begincontroller:wdtcntl端口映射(debugStates,系统时钟,SYSRST,WR,DATAIN,timerRestart,timer
- 2022-06-14 18:46:27下载
- 积分:1