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RX_RS_DEC
OFDM系统新型RS编解码的verilogHDL设计，经测试误码率性能提高(OFDM system verilogHDL new RS codec design, improved bit error rate performance tested)
- 2020-12-31 10:59:00下载
- 积分：1
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ov7670_sdram_vga_sobel
基于OV7670采集，SDRAM缓存，sobel处理，VGA显示的工程，内有全部代码，基于QUARTUS开发板实现。
FPGA 边缘检测(Based on OV7670 acquisition, SDRAM cache, sobel processing, VGA display project, with all the code, based on QUARTUS development board.
FPGA edge detection)
- 2019-04-23 17:31:00下载
- 积分：1
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2010-xilinx-fpga-
北京中教仪装备技术有限公司制作，关于xilinx FPGA使用的教程，包括ISE、picoblaze、microblaze等的使用说明。(some paper for the use of ise， picoblaze,microblaze)
- 2011-12-15 10:25:49下载
- 积分：1
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uart
实现与电脑端串行数据发送与接收，波特率为9600(Realize serial data sending and receiving with the computer terminal)
- 2017-10-04 01:30:01下载
- 积分：1
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一个latch3 VHDL编写。
A latch3 written in VHDL.
- 2022-04-15 06:24:21下载
- 积分：1
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vhdlcoder
VDHL的简单DEMO演示，有利于初学者学习使用(VDHL simple demo DEMO will help beginners learn to use)
- 2008-01-16 15:44:44下载
- 积分：1
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getCPU
获取主机CPU信息，VS2008编译通过，含详细说明(Get information on the host CPU, VS2008 compiler, containing detailed instructions)
- 2014-11-27 10:07:21下载
- 积分：1
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基于FPGA的OFDM信号传输系统VHDL源码
基于FPGA(Field-Programmable Gate Array)的OFDM(Orthogonal Frequency Division Multiplexing)信号传输系统VHDL源码
use IEEE.std_logic_unsigned.all;
package outconverter is
constant stage : natural := 3;
constant FFTDELAY:integer:=13+2*STAGE;
constant FACTORDELAY:integer:=6;
constant OUTDELAY:integer:=9;
function counter2addr(
counter : std_logic_vector;
mask1:std_logic_vector;
mask2:std_logic_vector
) return std_logic_vector;
function outcounter2addr(counter : std_logic_vector) return std_logic_vector;
end outconverter;
package body outconverter is
function counter2addr(
counter : std_logic_vector;
mask1:std_logic_vector;
mask2:std_logic_vector
) return std_logic_vector is
variable result :std_logic_vector(counter"range);
begin
for n in mask1"range loop
if mask1(n)="1" then
result( 2*n+1 downto 2*n ):=counter( 1 downto 0 );
elsif mask2(n)="1" and n/=STAGE-1
- 2022-02-13 14:58:13下载
- 积分：1
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Verilog实现 spi接口的FPGA实现 通过仿真，修改后即可应用
Verilog实现 spi接口的FPGA实现 通过仿真，修改后即可应用-Verilog realize spi interface FPGA to achieve through the simulation, the application can be modified
- 2022-08-14 13:03:16下载
- 积分：1
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sobel_edge_detect
sobel边缘检测，用于图像处理。实现了该算法在FPGA上的实现代码。(Sobel edge detection for image processing.Implementation of the algorithm to achieve the FPGA code.)
- 2016-07-17 21:54:26下载
- 积分：1
