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formal_verification
说明: 现在最流行的RTL设计方法之一,本书为全球流行的设计入门书籍(One of the most popular RTL design methods nowadays, this book is an introductory book for popular design all over the world.)
- 2020-06-23 22:00:02下载
- 积分:1
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adc0809的fpga时序电路接口程序
adc0809的fpga时序电路接口程序-Sequential Circuits adc0809 the FPGA interface program
- 2022-01-25 21:49:43下载
- 积分:1
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FPGA-基于fpga的PWM
一段很好地讲述PWM的VHDL硬件代码,可以在不同SOPC上运行实现
- 2022-01-30 19:23:51下载
- 积分:1
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CCD
本设计主要用来进行图像采集处理,通过摄像头采集图像信息,经过插值算法后存储到外部SDRAM,然后读取图像数据,进行边缘滤波处理后经VGA输出到屏幕上。(This design is mainly used for image acquisition and processing,through the camera capture image information,after interpolation to the external memory after the SDRAM,and then read the image data processed by the edge filter VGA output to the screen.)
- 2021-05-14 18:30:03下载
- 积分:1
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512×8bid的FIFO 含工程文件,基于QUARTUs
512×8bid的FIFO 含工程文件,基于QUARTUs-512 × 8bid the FIFO with the project document, based on the QUARTUsII
- 2022-03-14 07:41:33下载
- 积分:1
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闪烁的LED spartan3a一醒
应用背景建筑行为是counterled恒clk_50mhz_freq:整数:= 50000000;恒blink_freq:整数:= 1;恒cnt_max:整数:= clk_50mhz_freq / blink_freq / 2 - 1;恒blink_freq2:整数:= 8;恒cnt_max2:整数:= clk_50mhz_freq / blink_freq2 / 2 - 1;恒cnt_max3:整数:= clk_50mhz_freq / blink_freq * 2 - 1;信号CNT:符号(24到0);信号CNT2:符号(22到0);信号cnt3:符号(27到0);信号闪现:std_logic:=“1”;信号trigger_s:std_logic:=“0”;信号enableblink1s ;:std_logic:=“0”;开始过程(clk_50mhz)开始 ; ;如果(clk_50mhz = 1”和clk_50mhz"event)然后 ; ; ; ;trigger_s & lt;=触发;如果(不trigger_s触发)=“1”,然后enableblink1s & lt;=“1”;cnt3 & lt;=(别人= & gt;0);如果结束;如果enableblink1s =“1”,然后如果CNT2 = cnt_max2然后CNT2 & lt;=(别人= & gt;0);眨眼和不眨眼;其他的CNT2 & lt;= CNT2 + 1;如果结束;如果cnt3 = cnt_max3然后cnt3 & lt;=(别人= & gt;0);enableblink1s & lt;=“0”;其他的cnt3 & lt;= cnt3 + 1;如果结束;还有其他的;如果碳纳米管= cnt_max然后CNT & lt;=(别人= & gt;0);眨眼和不眨眼;其他的碳纳米管和碳纳米管+ 1;如果结束;如果结束;和,结束如果;和;结束过程;awake_led & lt;=眨眼;结束行为;关键技术图书馆的IEEE;std_logic_1164.all;std_logic_unsigned.all;numeric_std.all;counterled是端口(
- 2022-03-24 04:02:07下载
- 积分:1
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AES-on-FPGA
AES算法在FPGA上的实现,对AES算法所用的器件资源进行了总结(AES on FPGA the Fastest to the Smallest)
- 2014-12-31 10:06:46下载
- 积分:1
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Dice_game
VHDL Project for beginners. Electronic dice game. Perfect for Spartan devices.
- 2011-02-22 22:07:59下载
- 积分:1
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dpll
说明: 在quartus下搭建的数字锁相环,能实现频率自动跟踪。(The digital phase-locked loop built under quartus can realize automatic frequency tracking.)
- 2020-06-21 01:00:02下载
- 积分:1
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testbench
说明: altera 最新的CYCLONE IV的pci-e核的testbench,VHDL源程序。(altera latest CYCLONE IV of the pci-e core testbench, VHDL source code.)
- 2010-04-22 10:20:24下载
- 积分:1