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16位并行相关器的VHDL程序
16位并行相关器的VHDL程序-16 parallel with the VHDL-related procedures
- 2022-02-09 15:11:47下载
- 积分:1
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基于fpga和xinlinx ise 的7段码led显示程序,希望对你有所帮助
基于fpga和xinlinx ise 的7段码led显示程序,希望对你有所帮助-and ideally xinlinx 7 of the code led display program, and I hope to help you
- 2022-02-03 23:57:12下载
- 积分:1
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Verilog HDL编写的总线功能模型,十分有用,需要的下载
Verilog HDL编写的总线功能模型,十分有用,需要的下载-Verilog HDL prepared by the bus functional model is useful, it needs to download
- 2022-03-20 19:48:39下载
- 积分:1
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digital_clock
数字钟通过verilog实现,并且支持Modelsim仿真,通过实验验证(The digital clock is implemented by Verilog and supports Modelsim simulation)
- 2020-06-18 05:00:02下载
- 积分:1
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xilinx_usb_drivers_win10_x64
win10的xilinx usb驱动,较新版本(Xilinx USB driver for win10, newer version)
- 2021-03-11 17:09:26下载
- 积分:1
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sequenceur,该模块的主要功能是,控制器,在基本的risc架构中,实现各个模块的控制...
sequenceur,该模块的主要功能是,控制器,在基本的risc架构中,实现各个模块的控制-sequenceur,control
- 2022-11-21 05:05:03下载
- 积分:1
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A NiosII available LCD12864 IPcore, with examples
一个NiosII可用的LCD12864 IPcore,含例子-A NiosII available LCD12864 IPcore, with examples
- 2022-03-23 15:10:17下载
- 积分:1
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RS码译码器
采用VHDL语言实现基于BM算法的RS译码器,附件为整个工程文件,内附波形仿真图。程序在QUARTUS II 9.0下仿真通过
- 2022-06-03 16:19:45下载
- 积分:1
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project1
音乐计算器的设计与实现。完成加减与或比较计算,能显示进位借位零位,能根据结果的正负发出两首不同的音乐。(Design and implementation of music calculator. Complete addition and subtraction and comparison calculation, can display carry and borrow zero, can send out two different music according to the positive and negative results.)
- 2020-08-16 23:38:25下载
- 积分:1
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ads7846
四线电阻式触摸屏,ads7846控制显示触摸坐标(Four-wire Resistive Touch Panel, ads7846 touch control display coordinates)
- 2009-03-31 20:07:16下载
- 积分:1