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CD1_MT9V034_RAW_TRANS
基于FPGA的UDP网络图像传输实验，FPGA完成了MT9V034的RAW图像采集缓存，NIOS完成了图像的UDP封包，DM9000芯片完成了MAC和PHY的功能。(Based on the UDP FPGA network image transmission experiment, FPGA completed the RAW MT9V034 image acquisition cache, NIOS completed the image of the UDP packets, DM9000 chip MAC and PHY completed the function.)
- 2016-07-13 10:11:46下载
- 积分：1
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hilbert_transformer.tar
hilbert 变换的vhdl源代码，来源于网上，本人也做过简单的8抽头的，但这个的算法还没搞懂，希望懂行的下载了研究一下，给个中文的简单的说明！(hilbert transform VHDL source code from the Internet, I have been a simple 8-tap, but even before they get to know this algorithm, I hope knowledgeable downloaded to look for a simple description of the Chinese!)
- 2020-10-19 21:37:25下载
- 积分：1
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shape
基于FPGA的成型滤波器的代码，里面内附激励文件，使用verilog编写(FPGA-based shaping filter code, which included incentives files using verilog write)
- 2014-06-05 16:52:06下载
- 积分：1
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cntrlr
verilog code for bus controller
- 2014-03-19 15:17:24下载
- 积分：1
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基于fpga和xinlinx ise的音乐播放器vhdl程序，希望对你有所帮助！...
基于fpga和xinlinx ise的音乐播放器vhdl程序，希望对你有所帮助！-and xinlinx ideally music player VHDL process, and I hope to help you!
- 2023-02-07 05:35:03下载
- 积分：1
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A clock procedures, as well as stopwatch, I feel pretty good, there is a need to...
一个时钟程序，还有跑表，感觉相当不错的，有需要就下载吧-A clock procedures, as well as stopwatch, I feel pretty good, there is a need to download it
- 2022-03-12 05:29:00下载
- 积分：1
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smartWasher
QUARTER编程环境实现的智能洗衣机系统，通过DE0板子进行模拟，组要完成洗衣机5个步骤的顺序过程以及系统相应动作(QUARTER programming environment of intelligent washing system, through simulation DE0 board, groups 5 to complete the washing process and the system the sequence of steps corresponding action)
- 2020-11-06 13:19:49下载
- 积分：1
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JTAG_Example0_Verilog
一个Verilog的JTAG程序例子，包括完整的说明文档和源文件。(tap_top.v
This file is part of the JTAG Test Access Port (TAP)
http://www.opencores.org/projects/jtag/
Author(s): Igor Mohor (igorm@opencores.org))
- 2021-04-27 13:48:44下载
- 积分：1
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AMBA APB桥VHDL
这是一个AMBA APB桥实现VHDL。这包括主人，奴隶和试验台试验桥。我已经测试功能。
- 2022-06-02 20:02:44下载
- 积分：1
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基于FPGA的数字频率计设计
使用飓风开发板，完成了100M，频率计设计，并可在数码管显示
- 2022-02-25 11:23:58下载
- 积分：1
