登录
首页 » VHDL » SPI serial bus interface Verilog realization elaborate on the realization of the...

SPI serial bus interface Verilog realization elaborate on the realization of the...

于 2022-11-13 发布 文件大小:388.77 kB
0 74
下载积分: 2 下载次数: 1

代码说明:

SPI串行总线接口的Verilog实现,详细讲解实现过程。-SPI serial bus interface Verilog realization elaborate on the realization of the process.

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论


0 个回复

  • 按键控制led
    按键控制led灯亮灭顺序,从左到右跑或者从右往左跑(Press button to control the LED lights on and off)
    2017-06-30 10:37:30下载
    积分:1
  • chuankou
    本实验为UART回环实例,实验程序分为顶层unrt_top、发送模块uart_tx、接收模块 uart_rx,以及时钟产生模块clk_div。uart_rx将收到的包解析出8位的数据,再传送给 uart_tx发出,形成回环。参考时钟频率为100MHz,波特率设定为9600bps。(This experiment is an example of UART loop. The experimental program is divided into top-level unrt_top, sending module uart_tx, receiving module uart_rx, and clock generation module clk_div. Uart_rx parses the received packet into 8 bits of data and sends it to uart_tx to send out, forming a loop. The reference clock frequency is 100 MHz and the baud rate is set to 9600 bps. stay)
    2020-06-24 01:40:02下载
    积分:1
  • Altera DE2板专用CCD驱动器
    altera DE2 实验板专用 CCD驱动-altera DE2 board dedicated CCD driver
    2022-02-10 05:21:46下载
    积分:1
  • MCU_V_PWM_16bit
    单片机通过总线,将占空比和频率送到CPLD/FPGA中,并控制PWM输出.采用Verilog HDL语言编写。(Microcontroller by bus, the duty cycle and frequency sent to the CPLD/FPGA in, and control the PWM output. Using Verilog HDL language.)
    2020-10-29 09:19:57下载
    积分:1
  • test-bench
    如何编写测试文件,,test bench的编写方法和是列,,总结的非常好的东西(how to code test bench in verilog)
    2012-03-31 08:38:24下载
    积分:1
  • Verilog 编写的IP核,512K的16位SRAM
    Verilog 编写的IP核,512K的16位SRAM-Written in Verilog IP core, 512K 16-bit SRAM
    2023-01-13 23:15:04下载
    积分:1
  • yuqu
    蜂鸣器音乐演奏,有ppt说明,及实例工程文件。(Music buzzer, a ppt notes, and examples of engineering documents.)
    2020-12-27 20:09:02下载
    积分:1
  • AMBA-Bus_Verilog_Model
    说明:  该源码包是2.0版本的AMBA总线的Verilog语言模型,主要包括5个部分:AHB总线仲裁器,AHB-APB总线桥接器,AHB总线上从设备ROM模型,AHB总线上从设备RAM模型,参数定义。(This source code package is the model of V2.0 AMBA bus of ARM company, It mainly includes the following five parts: the AHB arbiter,AHB-APB bridge, AHB_Rom_Slave, AHB_Ram_Slave,Defines.)
    2021-04-25 21:48:46下载
    积分:1
  • Divider-vhdl
    This is a divider, which is depicted as well. It is a programming language Vhdl.
    2013-09-29 18:28:11下载
    积分:1
  • scope_VGA
    利用IIC接口的4路 ADC max1037,采集思路信号,通过在FPGA内部的构建DeltaSigma DAC软核,在VGA液晶显示屏上显示波形。 (IIC interface 4-way ADC max1037, collecting ideas signal the FPGA internal build DeltaSigma DAC soft-core VGA LCD display waveforms.)
    2012-07-24 00:41:29下载
    积分:1
  • 696518资源总数
  • 104887会员总数
  • 24今日下载