登录
首页 » VHDL » Altera DE2板专用CCD驱动器

Altera DE2板专用CCD驱动器

于 2022-02-10 发布 文件大小:11.23 MB
0 152
下载积分: 2 下载次数: 1

代码说明:

altera DE2 实验板专用 CCD驱动-altera DE2 board dedicated CCD driver

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • FPGA-DSP
    FPGA数字信号处理实现原理及方法的例程(FPGA digital signal processing principle and method routines)
    2017-05-31 10:36:17下载
    积分:1
  • Verilog HDL编写的总线功能模型,十分有用,需要的下载
    Verilog HDL编写的总线功能模型,十分有用,需要的下载-Verilog HDL prepared by the bus functional model is useful, it needs to download
    2022-03-20 19:48:39下载
    积分:1
  • DE2 will connect to the LCD layout for Terasic off technology companies attached...
    DE2将连接到LCD布局上,为Terasic off技术公司附上系统代码
    2023-02-16 06:25:03下载
    积分:1
  • Verilog_SimpleCalculator-master
    这是一个计算器的Verilog代码,可实现加减乘除等基础功能(calcultor for you to do some reserches.)
    2017-12-24 10:24:59下载
    积分:1
  • FPGA数字AGC(帮同学做的毕业设计)
    FPGA数字AGC(帮同学做的毕业设计)-FPGA digital AGC (help students to do the graduation project)
    2022-03-17 18:29:50下载
    积分:1
  • RS(204-188)decoder_verilog
    采用verilog实现的有限域GF(28)弱对偶基乘法器,本原多项式: p(x) = x^8 + x^4 + x^3 + x^2 + 1 ,多项式基: {1, a^1, a^2, a^3, a^4, a^5, a^6, a^7},弱对偶基: {1+a^2, a^1, 1, a^7, a^6, a^5, a^4, a^3+a^7}(Verilog achieved using the finite field GF (28) weak dual basis multiplier)
    2016-06-12 16:31:51下载
    积分:1
  • time_frequency
    这是一篇现代通信原理课程的作业报告.题目为几种时频分析方法比较及应用.详细介绍了短时傅里叶变换、小波变换、魏格纳—威利分布和Cohen类时频分布这4种典型时频分析方法,并作了比较(This is a modern communication Principle operating report. Entitled Comparison of several time-frequency analysis and 应用. 详细 Jieshao the short time Fourier transform, wavelet transform, Wigner- Willie distribution and frequency distribution of Cohen Lei This four kinds of typical time-frequency analysis method, and compared)
    2010-07-12 22:12:25下载
    积分:1
  • FPGA UART的发送等
    FPGA UART transmit and so on
    2022-01-24 13:54:39下载
    积分:1
  • 16位元浮点数CPU,可作运算,以VHDL编写
    16位元浮点数CPU,可作运算,以VHDL编写-16-bit floating point CPU, can be used for computing in order to prepare VHDL
    2022-05-17 06:20:07下载
    积分:1
  • Baseband_line_code
    基于VHDL语言的基带线路码产生电路设计(毕业论文),内涵完整的源代码(Based on VHDL language baseband line code generation circuit design (Thesis), meaning the complete source code)
    2010-07-03 22:38:09下载
    积分:1
  • 696516资源总数
  • 106415会员总数
  • 3今日下载