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                        ff_const_mul
                        
                          说明:  常系数有限域乘法器,verilog DHL源码(Constant coefficient finite field multiplier, verilog DHL source)                         
                            - 2011-02-19 21:09:36下载
- 积分:1
 
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                        ALU verilog
                        
                          无符号的并行乘法器的结构基于观察在增殖过程中的部分产品可以并行计算。
乘法运算的符号操作数,2 的补数系统中生成双长度的积。总体战略是累积的部分产品作为选定由乘数位添加版本被乘数。                         
                            - 2022-02-27 04:25:03下载
- 积分:1
 
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                        costas
                        
                          载波同步,costas环,基于Verilog的载波同步环(Carrier synchronization, costas ring, based on Verilog carrier synchronization ring 
)                         
                            - 2021-03-05 13:09:31下载
- 积分:1
 
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                        8.4-ADC0809-VHDL-control-program
                        
                          基于VHDL语言,实现对ADC0809简单控制(Based on VHDL language, to achieve the ADC0809 simple control)                         
                            - 2011-11-29 08:43:07下载
- 积分:1
 
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                        dividefrequency
                        
                          如何用VHDL语言对时钟进行分频以达到计数目的(how to achive counting by VHDL Language)                         
                            - 2009-02-13 15:45:38下载
- 积分:1
 
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                        usbFPGAconnect
                        
                          该例程是PC机通过FX2-CY7C68013-A的USB2.0控制芯片与FPGA实现通信。其中的工程和代码包括PC机上的USB固件程序、驱动程序、上位机程序,FPGA上的VERILOG通信程序。(The routine is a PC, through the FX2-CY7C68013-A of the USB2.0 controller chip and the FPGA to achieve communication. One of the projects and code, including PC, the USB firmware, drivers, FPGA' s Communication Program)                         
                            - 2021-04-08 15:19:00下载
- 积分:1
 
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                        MUX
                        
                          Multipleksor
3 to 1 - 3x1bit in,  1x1bit out                         
                            - 2013-09-18 16:21:25下载
- 积分:1
 
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                        基于MIPS指令集的32位CPU设计与Verilog语言实现_单周期CPU
                        
                          基于MIPS指令集的32位CPU设计与Verilog语言实现的单周期CPU,内含源代码和实验设计报告及实验仿真截图,与大家共享~                         
                            - 2023-07-31 04:30:04下载
- 积分:1
 
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                        widgets
                        
                          CSS配合jquery制作完美漂亮的时钟,貌似在IE8下时钟不能获取时间啊!支持ie9、chrome、safari、firefox、opera (Chrome显示效果最佳,IE9下时钟无法工作)日历和骰子是原创,CSS3时钟并非原创但经过改良支持opera。数字日历的兼容性不错,圆形时钟就差点了,也希望一起交流,共同改进。(CSS with the jquery make perfect beautiful clock, seemingly in IE8 under the clock can not get the time ah! Support ie9, chrome, safari, firefox, opera (Chrome show the best results, the clock does not work under IE9) calendar and dice is original, CSS3 clock is not original but after improved support opera. Digital calendar compatibility is good, almost round the clock on, and also hope together, and work together to improve.)                         
                            - 2014-10-31 09:25:37下载
- 积分:1
 
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                        shuzizhongsheji
                        
                          有用的数字钟设计文档,有秒表、闹钟等模块,希望对大家有用!(JUST LEARN FROM IT!!ENJOY!)                         
                            - 2013-07-18 11:02:24下载
- 积分:1