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并串转换
利用VHDL语言实现并串转换过程。利用VHDL语言实现并串转换过程。利用VHDL语言实现并串转换过程。利用VHDL语言实现并串转换过程。利用VHDL语言实现并串转换过程。
- 2023-06-03 10:20:03下载
- 积分:1
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sigmoid_FPGA
sigmoid函数硬件实现,verilog代码及其测试用例(Sigmoid function hardware implementation, verilog code and test cases)
- 2017-05-08 20:36:04下载
- 积分:1
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simple eight CPU, containing PDF files. They can check details
简单的8个CPU,包含PDF文件。他们可以查看详细信息
- 2022-07-03 13:41:23下载
- 积分:1
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interrupt
对于中断技术有非常详细的讲解,带图片完整版(Technology for the interruption of a very detailed explanation, with pictures full version)
- 2009-11-11 17:56:33下载
- 积分:1
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CPU_Project_board
CPU 5级流水线实现(加hazard处理与板级验证,板级验证带有按键消抖)(5-stage pipelined CPU (plus hazard dealing with board-level verification, board-level verification with key debounce))
- 2020-12-03 09:29:25下载
- 积分:1
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fft快速傅立叶变换源码
fft快速傅立叶变换源码-the source of fast fft transform
- 2022-06-14 17:04:07下载
- 积分:1
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SCAN_LED
基于EDA技术中的对LED扫描电路的实验,程序能成功运行,能直接在开发板上看实验结果(EDA-based LED technology to scan the experimental circuit, the program can run successfully, can see directly in the development of on-board results)
- 2009-06-05 11:49:53下载
- 积分:1
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zidong-shouhuoji
用VERILOG实现自动售货机功能,运行正确,希望有帮助(Use VERILOG implementation vending machine function, correct operation, hope to have help)
- 2014-01-05 20:42:49下载
- 积分:1
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URAT 部分VHDL源码 大家多多支持 哈哈
URAT 部分VHDL源码 大家多多支持 哈哈 -VHDL source URAT part of U.S. support of Haha
- 2022-02-20 22:56:56下载
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ar0134_1280x720P60
Camera AR0134详细的寄存器配置,以及配置顺序,可以用来初始化摄像头(Camera AR0134 detailed register configuration sequence )
- 2016-05-15 12:16:56下载
- 积分:1