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8bit的ALU实现
用vhdl语言编写的数字逻辑alu设计，实现包括逻辑运算乘法、加法和移位的运算功能，加入流水线处理，适用于初学硬件语言的同学们
- 2022-07-07 03:59:31下载
- 积分：1
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clock for spartan 3 evaluatoin board
clock for spartan 3 evaluatoin board
- 2022-02-28 19:30:52下载
- 积分：1
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sht30
温湿度传感器sht30驱动，系统时钟为125M可读出温湿度。(sht30 driver,sysclk=125MHZ)
- 2020-09-28 17:07:44下载
- 积分：1
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SG3525pinlvgenzong
采用SG3525实现感应加热电源的频率跟踪。(SG3525 is used to realize frequency tracking of induction heating power supply.)
- 2018-05-09 19:22:35下载
- 积分：1
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hilbert_transformer.tar
hilbert 变换的vhdl源代码，来源于网上，本人也做过简单的8抽头的，但这个的算法还没搞懂，希望懂行的下载了研究一下，给个中文的简单的说明！(hilbert transform VHDL source code from the Internet, I have been a simple 8-tap, but even before they get to know this algorithm, I hope knowledgeable downloaded to look for a simple description of the Chinese!)
- 2020-10-19 21:37:25下载
- 积分：1
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卡内基梅陇大学verilog课程讲义-unlocked
说明： verilog讲义
卡内基梅陇大学verilog课程讲义-unlocked
卡内基梅陇大学verilog课程讲义-unlocked(Verilog Course Lectures at Carnegie Mellon, University Verilog Course Lectures at Carnegie Mellon University Verilog Course Lectures at Carnegie Mellon University)
- 2020-06-20 18:00:02下载
- 积分：1
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Verilog语言编写的电话计费系统，这只是源代码，需要在quartusII等软件下运用...
Verilog语言编写的电话计费系统，这只是源代码，需要在quartusII等软件下运用-Verilog language telephone billing system, this is only the source code, the need to use software such as quartusII
- 2023-01-23 23:25:03下载
- 积分：1
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fifo
异步FIFO
输入: 16bit
输出:16bit
深度:256(Asynchronous FIFO
Input: 16bit
Output: 16bit
Depth: 256)
- 2017-07-10 14:02:36下载
- 积分：1
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fifoi
基于Xilinx Vertex2的可综合的2048x10位的读写可控制FIFO模块源代码，深度可控(Based on the Xilinx Vertex2 can be integrated 2048x10-bit read and write can control the FIFO module source code, the depth of controllable)
- 2008-12-19 00:17:51下载
- 积分：1
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can总线
说明： SJA1000的ip核和相关测试脚本,OPENCORES 下载(SJA1000 IP downloads from opencores)
- 2019-11-15 10:07:14下载
- 积分：1
