登录
首页 » VHDL » 黄金时段介绍STA

黄金时段介绍STA

于 2022-12-10 发布 文件大小:8.71 MB
0 111
下载积分: 2 下载次数: 1

代码说明:

PrimeTime Intro to STA -PrimeTime Intro to STA

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • UART_DMA
    UART_DMA的方法是使用nios实现UART方式实现DMA传输,在硬件平台上通过验证实现(UART_DMA way is to use uart dma transfer nios implemented in the hardware platform validated by)
    2020-11-03 10:39:53下载
    积分:1
  • This tutorial presents some basic concepts that can be helpful in debugging of a...
    This tutorial presents some basic concepts that can be helpful in debugging of application programs written in the Nios II assembly language, which run on Altera’s DE2 boards.
    2022-08-19 12:45:10下载
    积分:1
  • wallace_multiplier
    华莱士树乘法器,运用了华莱士树状结构和布斯算法,提高了速度(The Wallace tree multiplier uses the Wallace tree structure and the Buss algorithm to increase speed)
    2020-12-26 10:29:03下载
    积分:1
  • Polyphase--Filter
    多相抽取滤波器。分四相,两倍抽取,采用16阶FIR滤波器实现(Polyphase decimation filters. Divided into four phases, extracted twice using 16-order FIR filter implementation)
    2020-09-10 15:58:02下载
    积分:1
  • 国外经典verilog代码,很适合初学者,其中的有些概念对老手也可以考虑下...
    国外经典verilog代码,很适合初学者,其中的有些概念对老手也可以考虑下-Foreign classic Verilog code, it is suitable for beginners, of which some of the concept of a veteran may also want to consider under the
    2022-02-24 14:20:37下载
    积分:1
  • list_ch06_02_debounce
    Eliminate the program of key bounce
    2012-12-23 00:22:42下载
    积分:1
  • clock_6
    说明:  ds1302时钟驱动程序,已在quartus上验证可以是直接使用(DS1302 clock driver, which has been verified on quartus, can be used directly)
    2020-06-24 12:00:02下载
    积分:1
  • VGA的IP核,下载即可用,解压到指定目录下就可以了,参照里面的read me....
    VGA的IP核,下载即可用,解压到指定目录下就可以了,参照里面的read me.-VGA
    2022-02-02 20:02:28下载
    积分:1
  • SPI串口的内核实现spicore SPI串口的内核实现spicore
    SPI串口的内核实现spicore SPI串口的内核实现spicore-SPI string mouth essence realizes spicore the SPI string mouth essence to realize spicore the SPI string mouth essence to realize spicore
    2023-06-28 18:20:03下载
    积分:1
  • 基于FPGA 的usb传输
    利用FPGA实现USB芯片CY7C68013与上位机的进行通信的系统,代码采用VHDL语言实现,利用状态机实现FPGA控制USB的数据传输,传输时序采用SLAVE FIFO实现
    2022-03-05 23:47:35下载
    积分:1
  • 696518资源总数
  • 106164会员总数
  • 18今日下载