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dec
A Dec example written in VHDL.
- 2009-09-23 08:57:25下载
- 积分：1
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test-ram
design ram v8051 for project
- 2013-07-08 23:24:20下载
- 积分：1
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Documentation Of Digital Electronic Systems With VHDL from US DOD.
Documentation Of Digital Electronic Systems With VHDL from US DOD.
- 2022-05-09 12:50:24下载
- 积分：1
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坦克大战的演示程序 ，实现了基本的人机交互
坦克大战的演示程序 ，实现了基本的人机交互-Battle City demonstration program to achieve the basic human-computer interaction
- 2022-10-15 10:25:03下载
- 积分：1
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关于寄存器重命名register reallocation,VHDL
关于寄存器重命名register reallocation,VHDL-Register on rename register reallocation, VHDL
- 2022-02-09 20:31:31下载
- 积分：1
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xc2s100E FPGA的原理图
给想涉足FPGA的新人参考
xc2s100E FPGA的原理图
给想涉足FPGA的新人参考-xc2s100E FPGA schematic diagram of the FPGA would like to set foot in the new reference
- 2023-05-12 14:50:04下载
- 积分：1
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: Random pulse width modulation speed control system to solve the exchange of ac...
：随机脉宽调制是解决交流调速系统 中声学噪声的直接有效方法。随机零矢 量分 布是一种很好 的随
机方法，但其不对称的开关函数使其不适用于传统的电流采样方法。通过仿真表明 PWM周期中点采样的方
法无法得到准确的平均值，在分析不对称模式引起的纹波电流对电流平均值影响的基础上，提出了一种适合
于 RZV分布 的电流采样方法 。仿真结果证实该方法简单可行 。 -: Random pulse width modulation speed control system to solve the exchange of acoustic noise in a direct and effective way. Random zero vector distribution is a good random method, but the asymmetrical switching function so that it does not apply to the traditional current sampling methods. PWM cycle through the simulation shows that the mid-point sampling methods can not be an accurate, on average, the analysis of asymmetric mode ripple current caused by the impact on the current average value based on the proposed distribution of a suitable RZV current sampling methods. The simulation results confirmed that the method is simple and feasible.
- 2022-04-24 11:00:11下载
- 积分：1
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project_first
说明： basys3的数字钟，可以显示00.00-59.59(Digital clock of basys3,It can display 00.00-59.59)
- 2019-06-18 10:37:53下载
- 积分：1
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ODBC
ODBC编程实例，使用ODBC对基于开关量数据采集卡的通信接口设计与实现。(ODBC programming examples, using ODBC for data acquisition card based digital communications interface design and implementation.)
- 2013-07-14 13:16:35下载
- 积分：1
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Endat2_1_freq
用verilog实现endat2_1驱动,并用signalTap捕捉信号。(Using verilog achieve endat2_1 drive and use signalTap capture signal.)
- 2021-04-26 15:08:45下载
- 积分：1
