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frequency
数字频率计，测量范围0-1GHZ,测周测频自动转换，精度极高，花了很长时间，不过还是有一点点小问题，有待改进.(Digital frequency meter, range 0-1GHZ, automatic conversion measured weekly frequency measurement, high precision, took a long time, but still a little small problems to be improved.)
- 2011-08-11 00:51:18下载
- 积分：1
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Verilog_SimpleCalculator-master
这是一个计算器的Verilog代码，可实现加减乘除等基础功能(calcultor for you to do some reserches.)
- 2017-12-24 10:24:59下载
- 积分：1
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ozgul2013
说明： Digital pre-distortion (DPD) is an advanced digital
signal-processing technique that mitigates the effects of power
amplifier (PA) nonlinearity in wireless transmitters. DPD plays
a key role in providing efficient radio digital front-end (DFE)
solutions for 3G/4G basestations and beyond. Modern FPGAs
are a promising target platform for the implementation of flexible
wireless DFE solutions, including DPD.
- 2019-01-05 18:20:30下载
- 积分：1
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RISC
说明： URISC的RTL级设计，Verilog代码(Design: URISC RTL Verilog)
- 2019-06-16 23:07:39下载
- 积分：1
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marquee
Multisim11下8051跑马灯仿真。(The 8051 Marquee under Multisim11 simulation.)
- 2012-11-07 23:12:12下载
- 积分：1
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uartfifo使用fifo进行uart通信
使用verilog HDL语言进行编写，通过FIFO缓存，使用uart串口，与上位机进行通信。在本示例中，FPGA向上位机发送的数据每次加一，并在串口调试助手中显示，可以观察相关现象。
- 2022-02-21 18:02:35下载
- 积分：1
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LDPC最小和译码算法verilog代码
此部分verilog代码为ldpc的最小和译码算法verilog源代码。verilog源代码适用于Xilinx和altera开发环境。
- 2022-02-05 17:42:10下载
- 积分：1
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cntrlr
verilog code for bus controller
- 2014-03-19 15:17:24下载
- 积分：1
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MSK
FPGA中实现的MSK调制，带modelsim仿真。实际系统测试通过：载波和调制波信号频率可调。调制框图请参见樊昌信 通信原理247页(MSK modulation implemented in FPGA with modelsim simulation. The actual test system: a carrier wave signal and the modulation frequency is adjustable. See Fan Changxin modulation block diagram of communication theory 247)
- 2021-05-13 08:30:02下载
- 积分：1
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SDRAM
说明： SDRAM的驱动程序，主要是对SDRAM各类状态进行驱动，有刷新模块、读、写模块等。(The driver of SDRAM mainly drives various states of SDRAM, including refresh module, read and write module.)
- 2020-06-23 01:40:02下载
- 积分：1
