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SPI实现IP，用verilog实现
SPI实现IP，用verilog实现，结构清晰，其中包括verilog的源代码，设计说明文档
- 2022-01-28 17:04:07下载
- 积分：1
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007
给大家上传一本非常好的关于verilog-hdl的电子书，实用，易懂，易学。此为第七章(Give us a very good upload on verilog-hdl of e-books, practical, easy-to-understand, easy to learn. This is the Chapter VII)
- 2008-04-22 16:53:33下载
- 积分：1
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Writing-a-VHDL-Testbench
《编写VHDL测试概述》的英文原版讲述了如何使用VHDL写测试凳程序("Writing VHDL test overview" of the English original to write about how to use VHDL test bench program)
- 2014-04-03 21:57:01下载
- 积分：1
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con1
4 bit convoltion with vhdl.
- 2011-10-18 18:18:09下载
- 积分：1
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analogue-digi-ana-converter
design and implementation of a format conversion system on the Altera NIOS board(QUARTUS) which reads an analogue input, converts it into digital data, and then does the reverse conversion back into analogue format. This will be done by taking an analogue an analogue input using SPI MCP3202 12-Bit A/D converter to generate the digital data stream and then the digital data will be used to generate an analogue output using Analog Devices 8-bit SPI AD7303 D/A converter.
- 2009-08-04 21:23:05下载
- 积分：1
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or2a
使用vhdl语言设计一位全加器，在仪器上下载并实现LED灯的闪亮(A full adder design)
- 2013-09-26 18:24:15下载
- 积分：1
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CCMU
代码是一个复数乘法器，两个复数相乘，只用到了2个实数相乘，运算量少(Code is a complex multiplier, two complex multiplication, uses only real number multiplied by 2, operations less)
- 2011-11-04 11:56:47下载
- 积分：1
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verilogCRC32
32位bit输入的CRC32校验，verilog的代码，以及modelsim的testbench代码(The encode of CRC32 with 32bit-inputs based on verilog, and according encode of testbench)
- 2012-03-07 10:22:58下载
- 积分：1
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cnt60
60进制计数器,（由一六进制和十进制连线组成）(60 binary counter (hexadecimal and decimal by a connection form))
- 2011-11-29 10:48:37下载
- 积分：1
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ad9649的fpga驱动程序cf_ad9649_ebz_edk_14_4_2013_03_19
ad9649的fpga驱动程序,FMC接口，基于Xilinx KC705(AD9649 Evaluation Board, FMC Interposer & Xilinx KC705 Reference Design)
- 2020-06-28 14:00:02下载
- 积分：1
