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This is the design of the divider module EDA. Can achieve three different freque...
此为EDA设计的分频器模块。可以实现三种不同的频率信号，可以通过使用者自由设置频率大小-This is the design of the divider module EDA. Can achieve three different frequency signals, users can freely set the frequency of the size of
- 2022-07-22 16:48:57下载
- 积分：1
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64point_FFT
64点FFT代码 基4算法 Verilog(64-point FFT code radix-4 algorithm Verilog)
- 2021-01-15 09:48:46下载
- 积分：1
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16 点药材 4 FFT
16 点药材 4 FFT 与真正的价值。这被设计基于 Arduino 板和任何泰文 8 位微控制器创建的 c + + 代码。
- 2022-07-10 21:06:50下载
- 积分：1
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数字频率计
设计一简易数字频率计，其基本要求是：
1)测量频率范围0～999999Hz；
2)最大读数999999HZ,闸门信号的采样时间为1s；.
3)被测信号可以是正弦波、三角波和方波；
4)显示方式为6位十进制数显示；
5）具有超过量程报警功能。
5)输入信号最大幅值可扩展。
6）测量误差小于+-0.1%。
7)完成全部设计后，可使用EWB进行仿真，检测试验设计电路的正确性。(The basic requirements of designing a simple digital frequency meter are:
1) The measuring frequency range is 0-999999 Hz.
2) The maximum reading is 999999HZ, and the sampling time of gate signal is 1 s.
3) The measured signal can be sine wave, triangle wave and square wave.
4) The display mode is 6-bit decimal number display.
5) It has alarm function beyond range.
5) The maximum amplitude of input signal can be expanded.
6) The measurement error is less than +0.1%.
7) After completing all the design, EWB can be used to simulate and test the correctness of the circuit.)
- 2019-06-20 12:47:51下载
- 积分：1
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vhdl,十进制加减计数器，输出计数序列信号
vhdl,十进制加减计数器，输出计数序列信号-vhdl, decimal addition and subtraction counter, the output count sequence signal
- 2022-02-07 17:03:29下载
- 积分：1
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全部通过，是我的精心设计，完全满足初学者的要求。
全部通过，是我的精心设计，完全满足初学者的要求。-all passed, I was carefully designed, fully meet the requirements of beginners.
- 2022-02-20 15:52:11下载
- 积分：1
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FFT_FPGA_Verilog-master
xilinx ise开发环境中fft IP核调用，仿真(Xilinx ise development environment FFT IP core call, simulation)
- 2018-07-08 23:28:46下载
- 积分：1
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Xcell1
W elcome to X CELL, the new
Xilinx customer newsletter.
By sending us your development
system registration card you automatically
became n charter subscriber
to this quarterly publication. It is our
intent to make this an informative,
easy to read, responsive and-hopefully-
interactive newsletter. We
want to supply you with early and
correct information, tell you about
the status of our products and about
our plans, about bugs and their workarounds,
give you applications ideas
and convey to you some of the en thusiasm
that we feel for our Programmable
Gate Arrays.
If you have questions or suggestions,
please send them to me. II Letters
to the Editor make a newsletter
more lively.
Peter Alfke, Editor
- 2014-12-25 01:07:59下载
- 积分：1
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FPGA源代码
FPGA部分源代码，关于dsp48的应用，从一本很好的书上下的
- 2023-06-23 15:05:04下载
- 积分：1
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mvb_altera_may-02
altera mvb fpga sopc 设计参考文档，有一定价值(mvb fpga sopc Design scheme)
- 2015-01-15 17:15:33下载
- 积分：1
