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v3
说明： mojo v3 complete eagle schematic
- 2018-02-08 22:47:52下载
- 积分：1
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cpu
用全加器设计8位运算器逻辑电路图
2、根据逻辑电路用 VHDL编程实现
3、调试编译通过后，仿真
(this file can help you learn the design of cpu)
- 2010-01-05 09:56:11下载
- 积分：1
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my_lift
电梯控制，包括楼层按键相应，显示上下状态。(Elevator control, including the floors of the corresponding button to show the whole state.)
- 2008-04-24 10:15:52下载
- 积分：1
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tcd1209d
TCD1209D驱动程序
Verilog语言(TCD1209D driver Verilog language)
- 2021-04-08 09:49:01下载
- 积分：1
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TheResearchAndIPDesignOfSMBusBasedSmartBattery
本文研究了SMBus
规范，介绍了典型的基于片上系统（SoC）设计的知识产权核（IP）实现，采用自顶向下
(Top-down)的集成电路设计方法完成了设计，并架构了基于总线功能模型(BFM)的验证平台
完成功能仿真，顺利完成了逻辑综合和时序仿真。FPGA 验证和投片后测试均表明设计具有
良好的性能。(This paper studies the SMBus specification, based on the introduction of the typical system-on-chip (SoC) intellectual property core design (IP) implementation, using top-down (Top-down) of the integrated circuit design methods achieve a design and architecture based on the total Line functional model (BFM) achieve functional verification platform for simulation, successfully completed a logic synthesis and timing simulation. FPGA silicon validation and post-tests show that the design has good performance.)
- 2009-03-26 12:16:53下载
- 积分：1
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VHDLFIFO
用Verilog 写一个8x16 的FIFO，完成先入先出的功能，并且在FIFO读空时输出EMPTY
有效信号，读指针RP 不再移动；FIFO 写满时输出FULL 有效信号，并且即使WR 有效也
不再向存储单元中写入数据(写指针WP 不再移动)。
(NO)
- 2020-09-20 20:17:51下载
- 积分：1
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很多实用的例程，包括触发器，译码器，多路选择器
很多实用的例程，包括触发器，译码器，多路选择器-A lot of useful routines, including the flip-flop, decoder, MUX
- 2022-03-06 03:11:07下载
- 积分：1
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EncoderUsingif
encoder using else if statement
- 2015-05-21 13:41:00下载
- 积分：1
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PWM
使用VerilogHDL语言加上IP核产生PWM调制波，占空比和频率可调。(The PWM modulation wave, duty cycle and frequency can be adjusted by using VerilogHDL language and IP kernel..)
- 2015-06-05 10:29:28下载
- 积分：1
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Xilinx V5 FPGA详细规格、编程FPGA参考，系统设计…
detailed spec for Xilinx V5 FPGA, reference for programming of FPGA, system designer or ASIC designer.
- 2022-04-28 20:14:22下载
- 积分：1
