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fpga(CAN)
fpga实现ＣＡＮ总线控制器源码,每个项目都有说明文件，介绍使用方法。(fpga CAN Bus Controller source, each with explanatory documents on the use of methods.)
- 2020-11-26 15:09:31下载
- 积分：1
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MII bus verilog code
带DDR3内存条，HDMI，PCIE，SD，usb，i2c,spi,uart接口
- 2022-03-13 04:31:49下载
- 积分：1
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STM32F10x几种功能demo
STM32F107几种功能demo：串口，定时器，外部中断，systick，看门狗等实例
- 2022-03-21 00:47:07下载
- 积分：1
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fpga-fft
xlinx fpga实现fft功能，利用ip核，包含源程序及完整工程文件，直接就能使用(The fft function xlinx fpga ip-core contains the source code and complete the project file, and can be used directly)
- 2013-02-22 10:37:47下载
- 积分：1
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rgb1
红绿灯交通灯的设计，通过规定时间红绿灯的转变实现交通灯的控制(Traffic light traffic light design, implementation, control traffic lights traffic light changes by a predetermined time)
- 2017-01-09 09:07:58下载
- 积分：1
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I2C_code
与IP核配套的I2C-Master Core，包含了目前主流FPGA芯片的I2C实现，代码包括Altera/Xilinx/OpenCore等公司的VHDL/Verilog/C等。(I2C-Master Core)
- 2010-05-22 22:12:26下载
- 积分：1
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Xilinx vivado authoritative course
Xilinx vivado 权威教程，清华大学出版社出版，何宾编著。(Xilinx vivado authoritative course, published by Tsinghua University Press, edited by He Bin.)
- 2019-02-19 20:37:09下载
- 积分：1
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DDS
可以产生正弦波，三角波、锯齿波、方波，要求频率1Hz-100kHz，步进1Hz，具有自动扫频功能；
正弦波的相位可调，方波的占空比可调；
(Can generate sine wave, triangle wave, sawtooth wave and square wave, the required frequency of 1 hz- 100 KHZ, step 1 hz, with functions of automatic frequency sweep
The phase adjustable sine wave, square wave duty ratio is adjustable )
- 2021-05-07 02:58:36下载
- 积分：1
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fpuvhdl_latest.tar
浮点数运算的FPGA实现，包括仿真文件。(FPGA realization of floating-point operations, including the simulation file)
- 2009-09-05 11:20:12下载
- 积分：1
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CPU
运用vhdl硬件描述语言在quartus II开发环境下独立设计与实现了基于精简指令集的五级流水线CPU的设计与实现。该流水CPU包括：取指模块，译码模块，执行模块，访存模块，写回模块，寄存器组模块，控制相关检测模块，Forwarding模块。该CPU在TEC-CA实验平台上运行，并且通过Debugcontroller软件进行单步调试，实验表明，该流水线CPU消除了控制相关、数据相关和结构相关。(Using vhdl hardware description language development environment under quartus II design and implementation of an independent design and implementation of a five-stage pipeline RISC-based CPU' s. The water CPU include: fetch module, decoding module, execution modules, memory access module, the write-back module, the register set of modules, control relevant to the detection module, Forwarding module. The CPU in the TEC-CA experimental platforms, and single-step debugging through Debugcontroller software, experiments show that the pipelined CPU eliminates the control-related, data-related and structurally related.)
- 2020-09-21 10:37:53下载
- 积分：1
