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sparc org, vhdl rtl code
sparc org, vhdl rtl code
- 2022-04-19 15:34:55下载
- 积分:1
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VHDL
用VHDL语言实现一Mealy型时序电路,并做时序仿真和功能仿真检验正确与否。(Implement a Mealy-type sequential circuits using VHDL language, and do functional simulation and timing simulation test correct.)
- 2014-03-20 14:44:28下载
- 积分:1
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add_verilog
2位全加器,实现全加器的功能,有近位的加法,输出也有近位,还有testbench,进行验证,验证通过(Two full adders, to achieve full adder function, nearly bit adder, there are nearly bit output)
- 2014-05-14 18:56:33下载
- 积分:1
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receiver
一个LED大屏幕接收卡的完整设计工程,有需要学习LED大屏幕控制的朋友可以参考
- 2010-02-28 12:18:21下载
- 积分:1
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hand_shake
握手程序,可以完美实现跨时钟域的数据传输(handshake and testbench,verilog HDL)
- 2011-11-22 21:05:38下载
- 积分:1
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Avalon_VGA_Controller
基于ALTERA AVALON BUS 的 VGA Controller 设计(ALTERA AVALON BUS VGA Controller )
- 2014-09-23 21:07:40下载
- 积分:1
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ADS1115
本程序调试了TI的高精度模数转换芯片ADS1115,此模数转换器采用双积分型,16位,为IIC通信方式,调试较复杂,在对直流采集方面有着广泛的应用(This program debugging TI s high-precision analog-digital conversion chip ADS1115)
- 2013-08-23 22:49:26下载
- 积分:1
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AHDL
AHDL语言介绍,很详细的介绍AHDL语言介绍,很详细的介绍(AHDL language introduction, a detailed explanation)
- 2009-11-17 15:27:59下载
- 积分:1
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YCbCr2RGB
RGB 与YCbCr 颜色空间可以相互转化(RGB and YCbCr color space can be transformed into each other)
- 2016-05-01 11:11:43下载
- 积分:1
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用verilog语言写的串口通信程序,包括收发两个模块,可用于FPGA的通信中,可通过程序设置收发的位数,有很好的扩展性....
用verilog语言写的串口通信程序,包括收发两个模块,可用于FPGA的通信中,可通过程序设置收发的位数,有很好的扩展性.-Verilog language used to write serial communication program, including the sending and receiving two modules can be used for FPGA communications, you can send and receive through the program to set the number of bits, there is a very good scalability.
- 2022-06-17 10:57:04下载
- 积分:1