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这是一个在FPGA上实现CRC算法的程序,包含了CRC
这是一个在FPGA上实现CRC算法的程序,包含了CRC-8,CRC-12,CRC-16,CRC-CCIT,CRC-32一共五种校验形式。-err
- 2022-12-18 23:05:03下载
- 积分:1
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firhalfband
利用matlab提供的firhalfban函数设计阶数为16、通阻带容限为0.0001的半带滤波器。仿真测试滤波前后的信号时域图,回执滤波器的频率响应特性图(Provided firhalfban function using matlab design order of 16, through the 0.0001 stopband wool half-band filter. Simulation test filtered time domain signal before and after, receipt filter frequency response characteristic diagram)
- 2020-07-03 21:40:02下载
- 积分:1
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IIR
利用dsp builder设计的IIR滤波器,已经验证完全可以使用,只需要把其中系数改变。内含VHDL代码(Design IIR filters by dsp builder have been verified , just change the coffetions including VHDL code.)
- 2020-12-02 19:59:26下载
- 积分:1
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FPGA_design
成功解决FPGA设计时序问题的三大点.word说明文档,很详细(FPGA design timing problems successfully solved the three points)
- 2010-07-19 16:16:28下载
- 积分:1
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code
涉及到常用的模块,参数可配置,可以很方便的集成到应用中(Related to commonly used modules, parameters can be configured, can be easily integrated into applications)
- 2008-06-13 22:30:14下载
- 积分:1
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跑马灯程序FPGA
FPGA跑马灯程序,基于CPLD1270开发板的运用程序-Marquee program FPGA-based development board CPLD1270 the use of procedures
- 2022-02-04 16:36:32下载
- 积分:1
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sqrt_pipeline
Matlab - to hdl code for square root
- 2020-06-17 12:20:02下载
- 积分:1
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RANGEN
2011年全国大学生电子设计竞赛E题“简易数字信号传输性能分析仪”fpga的控制代码,verilog编写;包括了M序列及同步时钟的提取等所有程序。(2011 National Undergraduate Electronic Design Contest E title "Simple digital signal transmission performance analyzer" fpga control code, verilog prepared including the M-sequence and synchronous clock extraction and all other programs.)
- 2020-10-27 17:09:59下载
- 积分:1
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Flash-Memory-RAM
周立功Fusion StartKit,fpga开发板的实验例程,Flash Memory初始化RAM实验(ZLG Fusion StartKit, fpga development board test routines Flash Memory Initialize RAM experiments)
- 2013-03-07 20:36:48下载
- 积分:1
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抢答器仿真
本文件包括整个基于QuartusII实现的抢答器模块,其下包括各个分模块,实现效果较不错。
- 2022-08-10 14:21:30下载
- 积分:1