登录
首页 » VHDL » 过滤多相

过滤多相

于 2022-02-22 发布 文件大小:22.81 kB
0 152
下载积分: 2 下载次数: 1

代码说明:

我的项目执行 filtrage 和抽取使用多相分解,在这种情况下,抽取因子被带到 5,所以筛选器由 5 集团过滤器和每个 oprates 在频率采样除以 5

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • clock_FPGA_verilog
    简易电子钟的设计(verilog HDL)(Simple design of the electronic clock (verilog HDL))
    2012-11-03 10:35:49下载
    积分:1
  • BT656_RGB
    将BT656数据流转换成RGB图像格式的数据(Converting BT656 data stream into RGB image format)
    2021-03-22 09:29:17下载
    积分:1
  • class17_TLC5620
    TLC5620驱动程序包括其他文件,8位,4通道,电压输出型DAC的数模转换器(TLC5620 driver and doc)
    2018-08-13 16:58:54下载
    积分:1
  • chengxu
    设计制作一个可容纳4组参赛者的数字智力抢答器,每组设置一个抢答按键; 电路具有一第一抢答信号的鉴别和锁存的功能。在主持人将系统复位并发出抢答指令后,若参加者按抢答键,则该组指示灯亮并用组别显示抢答者的组别。此时,电路具有自锁功能,使别组的抢答开关不起作用。 设置计分电路。每组在开始时预置成6分,抢答后主持人计分,答对一次加1分。(The design can accommodate a the Entrants digital intellectual Responder, each set answer in a key circuit has a first answer in the signal to identify and latch functions. Host to the system reset and sent the answer in instruction, participants answer in key, the group of the group light and display the answer in the group. At this point, the circuit has a self-locking function does not work in other groups to answer switch. Set Scoring circuit. Preset six points each at the beginning of the answer in scoring after the host, answer time, add 1 point.)
    2012-06-10 12:58:44下载
    积分:1
  • I2CVHDLASDASDADASD
    内容太短。注意请: 代码没有很好的描述将被删除,你不会得到任何点。请描述一下更好地获得更多积分。
    2022-11-26 06:20:03下载
    积分:1
  • AXI-full
    axi协议中的full子协议,可用于直接访问zynq器件的ddr器件。(The full sub protocol in the Axi protocol can be used to direct access to the DDR device of the zynq device.)
    2018-03-15 10:40:55下载
    积分:1
  • zobrazenie_16_bit_cisla_paralel
    16 bit switch input view in hexa format on 7seg display
    2013-08-16 00:50:49下载
    积分:1
  • QAMMod
    QAM调制,解调matlab代码,包含BPSK,QPSK,16QAM,64QAM,256QAM,1024QAM,4096QAM。其中调制方式。代码通过验证。(QAM modulator,demodulator)
    2020-10-26 16:59:59下载
    积分:1
  • FPGA_homewrk4
    设计一个能求出一个32bit字中两个相邻0之间最大间隙的电路。完成HDL设计及testbench描述,给出综合后的时序仿真结果。提交纸质文档。(Design a circuit that can find the maximum gap between two adjacent 0 in a 32bit word. The HDL design and testbench description are completed, and the result of comprehensive simulation is given. Submit paper documents.)
    2018-05-07 17:54:12下载
    积分:1
  • 用Verilog HDL实现I2C总线功能,对I2C总线有很大帮助
    用Verilog HDL实现I2C总线功能,对I2C总线有很大帮助-I2C bus contrll functions implemented by Verilog HDL.
    2022-06-01 23:07:46下载
    积分:1
  • 696518资源总数
  • 105895会员总数
  • 18今日下载