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C54x is the Verilog code opencoreip
c54x的VeriLog程序代码
也是opencoreip-C54x is the Verilog code opencoreip
- 2022-03-26 18:08:34下载
- 积分：1
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Uses Verilog the HDL design, obtains the realization basis on
the palm space int...
采用Verilog HDL设计,在掌宇智能开发板上得到实现
根据抢答器的原理，整个电路可划分为三部分：采样电路、门控电路和译码电路- Uses Verilog the HDL design, obtains the realization basis on
the palm space intelligence development board to snatch the answering
principle, the entire electric circuit may divide is three parts: The
sampling electric circuit, the gate control the electric circuit and
the decoding circuit
- 2022-03-16 23:36:15下载
- 积分：1
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ex11
说明： 该模块实现了FPGA的uart串口收发功能(The module realizes UART serial port transceiver function of FPGA)
- 2020-09-09 11:58:09下载
- 积分：1
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运行在FPGA上的Verilog程序(实现对ADC的控制)
运行在FPGA上的Verilog程序(实现对ADC的控制)-Verilog procedures (the achievement of the control of the ADC)
- 2022-01-30 10:06:47下载
- 积分：1
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AD-conversion-using-LTC1298
AD conversion using LTC1298
- 2012-06-06 15:26:41下载
- 积分：1
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9850sin_function
ad9850函数发生器 MSP430单片机驱动程序 扫频 DDS(AD9850 DDS)
- 2013-08-27 15:13:29下载
- 积分：1
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FPGA Verilog HDL模拟IIC通讯接口
FPGA Verilog HDL模拟IIC通讯接口-FPGA Verilog HDL IIC Interface
- 2023-04-25 13:55:03下载
- 积分：1
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turbo_encode
turbo码的编码程序,verilog HDL,在ISE环境中(turbo code encoding process)
- 2014-03-29 15:09:58下载
- 积分：1
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串uart的vhdl，verilog，lattic实现原码
里面有四个文件,分别UART 源码 (lattice version)uart 源码 (Veri...
串uart的vhdl，verilog，lattic实现原码
里面有四个文件,分别UART 源码 (lattice version)uart 源码 (Verilog)uart 源码 (VHDL)uart16550.tar-uart series of vhdl and verilog. lattic achieve the original code, there are four documents, Source respectively UART (lattice version) uart source (Verilog) uart source (VHDL) uart16550.tar
- 2022-04-12 23:45:53下载
- 积分：1
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用VHDL硬件描述语言开发的miniUART接口IP Core,用户可以将其嵌入到自己的FPGA模块中。...
用VHDL硬件描述语言开发的miniUART接口IP Core,用户可以将其嵌入到自己的FPGA模块中。-VHDL hardware description language developed by miniUART Interface IP Core, Users can be embedded into their own FPGA module.
- 2022-10-05 02:20:03下载
- 积分：1
