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log10(x)
Fixed-point base-2 logarithm (DW_log2)
// Computes the base-2 logarithm of a fixed point value in the
// range [1,2).
- 2014-09-11 19:58:10下载
- 积分：1
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zidong-shouhuoji
用VERILOG实现自动售货机功能，运行正确，希望有帮助(Use VERILOG implementation vending machine function, correct operation, hope to have help)
- 2014-01-05 20:42:49下载
- 积分：1
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利用verilog语言设计实现8路FIR滤波
利用verilog语言设计实现8路FIR滤波-Using verilog Language Design and Implementation of 8-channel FIR filter
- 2022-01-26 16:41:16下载
- 积分：1
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QAM16_demo
This is a demonstration for 16QAM. It is a Simulink model, including hardware implementation on Xilinx FPGA for adaptive equalizer and carrier recovery.
- 2010-11-09 03:00:52下载
- 积分：1
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标准电视信号的同步生成程序，利用VHDL和原理图，利用Quartus综合...
标准电视信号的同步生成程序，利用VHDL和原理图，利用Quartus综合-Standard television signal to generate the synchronization procedures, the use of VHDL and schematic diagram, using Quartus integrated
- 2022-03-13 05:08:34下载
- 积分：1
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world clock
世界时钟，最简单的vhdl的fpga设计，是vhdl语言的入门级，jigon供参考娱乐
- 2022-01-28 20:54:25下载
- 积分：1
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that I wrote four string and turn ISE code In xilinx Spartan3E debugging has bee...
这是我自己写的4位并转串ISE代码，在xilinx Spartan3E 上已经调试成功，拿出来与大家分享！-that I wrote four string and turn ISE code In xilinx Spartan3E debugging has been successful, with the show to share with you!
- 2022-02-14 20:17:51下载
- 积分：1
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VGA采用Spartan 3E板系统的VHDL
Vga in vhdl using spartan 3e board basys
- 2023-04-03 19:05:04下载
- 积分：1
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hdl_adder
说明： MATLAB to HDL Code conversion
- 2020-06-17 12:40:01下载
- 积分：1
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mdio
用VIVADO软件编写的，实现以太网芯片88E1510中的mdio控制模块代码，并且含有VIO仿真文件(Written in VIVADO software, the realization of the Ethernet chip 88 e1510 mdio control module of code, and contains the VIO simulation file)
- 2020-09-16 14:37:55下载
- 积分：1
