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I121-v1.10
Implementation of Serial Infrared decoder for low-speed IrDA communications.
- 2013-06-14 05:38:14下载
- 积分:1
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verilog_curr_design
说明: 实现中采用 Verilog HDL 描述、 ModelSim 进行功能仿真、 Quartus II 进行逻辑综合和适配下载(Design of table tennis game machine)
- 2020-07-16 21:49:36下载
- 积分:1
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一位十进制可逆计数器的Verilog代码
Verilog实现的一位十进制可逆计数器,可以实现十进制数的加减功能,有仿真图,计数器模数为10,有计数器使能控制,进位输出,具有同步置数和异步清零功能
- 2022-03-15 17:20:35下载
- 积分:1
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blocking
基于verilog语言的数据选择器,包括数据选择器的测试模块
(verilog language based on the data selector, including data selection for the test module)
- 2007-03-22 09:05:10下载
- 积分:1
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rscode
RS编码器在fpga上的实现,用的modelsim开发环境(RS encoder in the realization of the fpga, development environment used in modelsim)
- 2009-06-11 21:45:49下载
- 积分:1
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telephone-cost-metering
该程序用来实现电话计时以算取费用,比较简单(telephone cost metering verilog code)
- 2013-11-03 19:45:00下载
- 积分:1
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fpga2
FPGA学习的非常好的资料,希望广大朋友都可以学习学习啊(FPGA to learn very good information, I hope our friends can learn ah)
- 2013-05-28 22:09:28下载
- 积分:1
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[verilog]dcfifo_256x32
双时钟域FIFO(This is self-defined Dual-Clock FIFO, using logic lut resources.
Dual-Clock FIFO,
Depth: 256
Width: 32
USEDW: Y
FULLL:Y
EMPTY:Y)
- 2017-05-10 13:25:41下载
- 积分:1
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ModelSim_
FPGA编写环境,具有仿真容易,软件内存小的特点(FPGA authoring environment, with easy simulation software features small memory)
- 2013-07-24 19:20:57下载
- 积分:1
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AWGN_VerilogDesign-master
加性高斯白噪声生成的VERILOG实现,包含所有的testbench文件。可直接使用(Additive white gaussian noise generated VERILOG realized, including all testbench files. Can be used directly)
- 2021-01-14 19:18:46下载
- 积分:1