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ddr3_test
说明： 通过循环读写DDR3内存，了解其工作原理和DDR3控制器的写法，由于DDR3控制复杂，控制器的编写难度高，这里笔者介绍XILINX的MIG控制器情况下应用，是后续音频、视频等需要用到SDRAM实验的基础。(Through reading and writing DDR3 memory circularly, we can understand its working principle and the writing method of DDR3 controller. Because of the complexity of DDR3 control, it is difficult to write the controller. Here, the author introduces the application of Xilinx's MIG controller, which is the basis of SDRAM experiment for subsequent audio and video.)
- 2021-04-16 10:00:15下载
- 积分：1
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read-string-from-FLASH
read data of type character from flash memory
- 2013-09-08 03:49:15下载
- 积分：1
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带LDN的的同步的预置数端子，并且带CLR的异步清零端
带LDN的的同步的预置数端子，并且带CLR的异步清零端-LDN synchronization with the preset number of terminals, and cleared with CLR Asynchronous client
- 2022-02-22 00:30:35下载
- 积分：1
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audio_verilog
AUDIO音频模块AN831的录音及播放FPGA代码，测试通过(AUDIO audio module AN831 recording and playback of FPGA code, the test passed)
- 2020-09-12 09:27:58下载
- 积分：1
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I2C verilog 源代码 非常好的代码，大家可以
I2C verilog 源代码 非常好的代码，大家可以-I2C verilog source code for a very good code, we can
- 2022-03-14 16:49:14下载
- 积分：1
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shape
基于FPGA的成型滤波器的代码，里面内附激励文件，使用verilog编写(FPGA-based shaping filter code, which included incentives files using verilog write)
- 2014-06-05 16:52:06下载
- 积分：1
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高阶矩阵奇异值分解的FPGA实现方法svd_fpga
一种计算高阶矩阵奇异值分解的FPGA实现方法。(A high-end computing matrix singular value decomposition of the FPGA realization method.)
- 2020-07-07 12:28:57下载
- 积分：1
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编译实现循环码的产生，用FOR循环分别对其中的码元进行设置。...
编译实现循环码的产生，用FOR循环分别对其中的码元进行设置。-Implementation cycle of the compiler generated code, respectively, using FOR Cycle one of the key element of the set.
- 2022-08-11 07:55:45下载
- 积分：1
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verilog
基于QUATEUS2的设计一个8位频率计verilog语言编程(The design is based QUATEUS2 an 8-bit frequency counter verilog programming language)
- 2011-12-01 20:19:48下载
- 积分：1
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使用vhdl语言实现对led的控制，还有电路仿真
使用vhdl语言实现对led的控制，还有电路仿真-Using vhdl language implementation of the led control, as well as circuit simulation
- 2022-03-12 11:40:55下载
- 积分：1
