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turbo_dinter
说明： 电网协议信道解交织器设计FPGA实现，适用于PB16的宽带电力线载波通信(Grid protocol channel deinterleaver design FPGA implementation, suitable for PB16 broadband power line carrier communication)
- 2020-05-08 15:53:18下载
- 积分：1
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DPD_project
预失真算法中，包络解波部分的verilog代码，有部分错误(envelope calculation of DPD algorithm ，verilong HDL language)
- 2014-04-26 15:45:21下载
- 积分：1
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jesd204_0_ex
说明： jesd204b接收部分程序和带仿真历程(Jesd204b receiving part program and simulation process)
- 2020-11-26 14:49:31下载
- 积分：1
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cla - Copy
ADDER USING VERILOG ADDER WITH VERILOG VERILOG ADDER
- 2019-03-19 01:35:37下载
- 积分：1
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16QAM
基于FPGA 16QAM解调verilog代码，(16QAMdemoluator veriliog)
- 2021-02-23 23:49:39下载
- 积分：1
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ov7670_sdram_vga_sobel
说明： 基于OV7670采集，SDRAM缓存，sobel处理，VGA显示的工程，内有全部代码，基于QUARTUS开发板实现。
FPGA 边缘检测(Based on OV7670 acquisition, SDRAM cache, sobel processing, VGA display project, with all the code, based on QUARTUS development board.
FPGA edge detection)
- 2019-04-23 17:31:00下载
- 积分：1
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dianzhen
fpga实验板上16*16点阵显示汉字的程序-翻译结果fpga实验板上16*16点阵显示汉字的程序(Experimental fpga board 16* 16 dot matrix display Chinese program- translation results fpga experimental board 16* 16 dot matrix display Chinese characters in the program)
- 2013-12-24 16:28:00下载
- 积分：1
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verilog-code-style-specification
企业用verilog代码风格规范 本规范规定了IC设计项目开发过程中VerilogHDL源代码的编写总则、要求及模板文件。(Enterprises with verilog code style guide for the preparation of this specification General IC design project development process VerilogHDL source code, requirements and template files.)
- 2015-05-31 16:06:37下载
- 积分：1
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VHDL_example_100
本书通过100个实例，详细介绍便件描述语言vHDL的各种语法现象及其在专用集成电路(AHc)设计蝴还中的使用方法。(the book through one hundred examples, it detailed description language vHDL pieces of the phenomenon and its various grammatical in ASIC (AHc) were also designed butterfly The usage.)
- 2007-03-25 09:57:05下载
- 积分：1
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license
quartus license dede(quartus 11.0 license)
- 2014-04-21 18:26:12下载
- 积分：1
