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                        FPGA_design
                        
                          成功解决FPGA设计时序问题的三大点.word说明文档,很详细(FPGA design timing problems successfully solved the three points)                         
                            - 2010-07-19 16:16:28下载
- 积分:1
 
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                        Verilog-design-and-identify-book
                        
                          找到这本书的完整版了。呵呵,贴出来和大家共享。这是本好书,我买了一本作为Verilog的参考书。这本书语法部分集中,便于查阅,此外讲了很多实用的设计思想。最重要的是本书薄,可以完整看完。强烈推荐。
(如果只是查阅,电子版就可以,如要完整学习,建议还是买纸质版的)(Find the full version of this book. I posted and share. This is a good book, I bought a reference book as Verilog. Syntax in this book section focuses on ease of reference, in addition to speaking a lot of useful design ideas. The most important thing is that the book is thin, you can complete reading. Highly recommended. (If you only access the electronic version to complete learning, suggestions or to buy the paper version))                         
                            - 2012-06-07 21:58:19下载
- 积分:1
 
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                        通用RS编码
                        
                          RS通用编码器,根据定义的参数以及本原多项式就能实现各种体制的编码,Verilog实现,还附带有限域乘法的实现,代码清晰,精炼                         
                            - 2022-08-15 10:45:57下载
- 积分:1
 
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                        lab12_design_files
                        
                          des code source  vhdl sur fpga                         
                            - 2016-03-29 08:09:05下载
- 积分:1
 
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                        progconterful
                        
                          four bit counter verlog source code   for veriwell including  test bench                         
                            - 2010-03-29 18:54:45下载
- 积分:1
 
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                        1_Carm
                        
                          经典的OV5642的verilog驱动程序(Verilog Driver of Classic OV5642)                         
                            - 2019-03-19 13:38:29下载
- 积分:1
 
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                        cpu32 _加法器
                        
                          介绍 verilog 语言,用于实现包括乘法计算两个 32 位数字。在码,我输入我的 CWID 和 41411 来验证功能。您可以更改要计算不同的值的十六进制文件。体系结构 ︰ 携带-波纹 + 进位跳跃。                         
                            - 2022-12-10 02:15:03下载
- 积分:1
 
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                        Verilog HDL 频率可调的任意波形发生器
                        
                          Verilog HDL数字系统设计项目,频率可调的任意波形发生器,可以输出正弦波、方波、三角波和反三角四种波形(Verilog HDL digital system design projects, adjustable frequency arbitrary waveform generator can output sine wave, square wave, triangle wave and the anti-triangular four waveform)                         
                            - 2011-05-08 03:21:34下载
- 积分:1
 
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                        xilinx-timing-constrains
                        
                          ISE时序约束笔记——Global Timing Constraints,这个文档中详细介绍了如何使用ISE中约束工具和原理,对fpga水平提高有很大帮助(In this file , global timing constraints is introduced very clearly. It can really helps)                         
                            - 2012-04-16 11:08:45下载
- 积分:1
 
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                        fpga_ofdm
                        
                          这是篇<基于FPGA 的OFDM 宽带数据通信同步系统设计与实现>, 觉得甚是有用,大家共同学学。(This is the article <FPGA-OFDM-based broadband data communication systems design and implementation of synchronous> that even be useful, we all learn together.)                         
                            - 2007-06-13 00:02:43下载
- 积分:1