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在FPGA高速ADC-ADC08D1000沟通
这是由阿龙利开发的程序，以控制ADC08D1000模拟 - 数字设备中的FPGA，赛灵思的Virtex-4 SX35 FPGA此处应用，DCM的用于控制FPGA中的时钟路径，所述时钟源是AD9517该PLC控制的FPGA中的串行端口
- 2022-01-25 18:39:36下载
- 积分：1
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BRAT
early branch rename table(store rename table once the branch instruction comes in. Used in out of order pipeline processor)
- 2012-03-27 15:15:08下载
- 积分：1
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E1 (FIRST ORDER EUROPE TRANSMISSION STANDARD)qw
E1 (FIRST ORDER EUROPE TRANSMISSION STANDARD)qw
- 2023-06-23 08:30:04下载
- 积分：1
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wireless_communication_FPGA
数字化，宽带化，是当今无线通信的重点主流方向，FPGA以其功能强大，开发周期短，投资少，可重复修改，开发工具智能及软件可升级等特点成为无线通信首选。(Digital, broadband, is the focus of today s mainstream wireless communications, FPGA with its powerful, short development cycle, low investment, repeatable modify, intelligence and software development tools and other characteristics can be upgraded to become the first choice of wireless communication.)
- 2015-01-30 22:03:45下载
- 积分：1
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A-VLSI-PROGRESSIVE-CODING-FOR-WAVELET-BASED-IMAGE
this is fpga based vhdl coding and report for wavlet based image compression in vhdl
- 2012-01-13 18:00:29下载
- 积分：1
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LIP2242CORE_otp_rom
Verilog OTP ROM source code
- 2011-01-31 09:54:45下载
- 积分：1
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ethernet_udp_ep4c_ok_final
用ALTERA的FPGA实现UDP通信源代码(FPGA UDP)
- 2015-04-27 01:15:36下载
- 积分：1
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LMS算法FPGA仿真
说明： 自适应滤波器算法LMS ，的FPGA实现，采用VERILOG实现。(LMS, an adaptive filter algorithm, is implemented on FPGA and VERILOG.)
- 2020-06-24 01:00:02下载
- 积分：1
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(2,1,9)卷积编解码器，译码部分采用Vitebi译码算法，设计使用Verilog HDL语言，在Modelsim平台下仿真通过
(2,1,9)卷积编解码器，译码部分采用Vitebi译码算法，设计使用Verilog HDL语言，在Modelsim平台下仿真通过-(2,1,9) convolutional codec, decoding part decoding algorithm used Vitebi design using Verilog HDL language simulation in ModelSim platform through
- 2022-05-25 02:39:25下载
- 积分：1
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Verilog代码。注册成功，对FPGA的使用标准单元库…
verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.-Verilog code. Certified success, as a standard cell library for the use of FPGA designers.
- 2022-06-15 14:54:08下载
- 积分：1
