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systolic
实现QR_RLS算法,基于fpga
的非线性功放的dpd实现(realize QR_RLS)
- 2012-02-24 10:07:34下载
- 积分:1
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Study the performance of state machine. Rar inspect the performance of state mac...
状态机的性能考察.rar
状态机的性能考察.rar-Study the performance of state machine. Rar inspect the performance of state machine. Rar
- 2023-04-13 19:15:04下载
- 积分:1
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Hamming
汉明码转换,在FPGA上用verilog实现(hamming encoder, using FPGA)
- 2011-05-22 09:46:09下载
- 积分:1
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edk91i_mb_ref_guide
embedded development kit 9.1 user guide
- 2009-05-22 19:17:10下载
- 积分:1
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dec2_4
decoder 2-4
digital core
- 2016-05-20 03:50:28下载
- 积分:1
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增强的音频工程
Enhanced Audio Project
by
Dixie Xue & Wei Zhang
-Enhanced Audio Project
by
Dixie Xue & Wei Zhang
- 2022-08-26 07:09:41下载
- 积分:1
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Altera Sdram IP 源码,VHDL写的
Altera Sdram IP 源码,VHDL写的-Altera Sdram IP source code, VHDL written
- 2022-04-21 21:08:22下载
- 积分:1
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FFT程序,此程序虽然耗逻辑资源很大,但是在接受数据后的第7个时钟沿就可以输出FFT变换后的数据,对要求时延较低的系统可以考虑...
FFT程序,此程序虽然耗逻辑资源很大,但是在接受数据后的第7个时钟沿就可以输出FFT变换后的数据,对要求时延较低的系统可以考虑-FFT procedure, this procedure should not consume a lot of logic resources, but the data in the first seven clock can be output along the FFT transformed data, the requirements of time-delay system can be considered lower
- 2022-05-13 18:56:56下载
- 积分:1
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d ,t flip flop
该程序是在d,t,jk触发器上用vhdl语言编写的
- 2022-08-23 17:17:57下载
- 积分:1
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一个用Verilog编写的编帧、解帧及码速匹配的程序,相当经典
一个用Verilog编写的编帧、解帧及码速匹配的程序,相当经典-Verilog prepared with a series of frames, frames and solutions yards speed matching procedures, rather classic!
- 2023-02-12 02:50:03下载
- 积分:1