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fpga1
说明： 基于EasyFPGA030的直流电机控制电路设计和四位数字密码锁。(DC Motor Control Based on EasyFPGA030 circuit design and four-digit combination lock.)
- 2010-05-03 20:20:42下载
- 积分：1
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CAN
说明： ZYNQ中 PS 端 CAN接口的基本使用方法，并通过 CAN接口实现与 PC 端 CA N调试软件之间的数据接收和发送(The basic use method of PS end can interface in zynq, and the data receiving and sending with PC end can debugging software through can interface)
- 2020-04-03 16:41:52下载
- 积分：1
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Block-cipher-lock
密码锁verilog源代码，包括四个七段数码管显示模块，设置密码以及输入密码校验模块(Password lock Verilog source code, including four of seven digital tube display module, set the password and password verification module)
- 2014-01-11 23:57:19下载
- 积分：1
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LDPC码的消息节点（Bitnode）消息更新过程的VHDL语言实现
LDPC码的消息节点（Bitnode）消息更新过程的VHDL语言实现-LDPC code of the message node (Bitnode) news update process of the VHDL language
- 2022-12-16 00:40:03下载
- 积分：1
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OFDM_802_11
ofdm的发射链路和接收链路的Verilog源代码，包括长短训练序列的生成，导频插入，加cp，ifft。(Source code of transmission link and reception link of OFDM)
- 2020-12-22 21:19:06下载
- 积分：1
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sm4_Verilog
sm4 VERILOG 代码实现及其在无线网络3G中的应用(sm4 VERILOG)
- 2020-08-11 20:58:27下载
- 积分：1
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hdl_adder
MATLAB to HDL Code conversion
- 2020-06-17 12:40:01下载
- 积分：1
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this a spartan 3E base project file.
this is the project of game in which vga...
this a spartan 3E base project file.
this is the project of game in which vga is interfaced to FPGA.
this file is main file in which vga timing is maintained.-this is a spartan 3E base project file.
this is the project of game in which vga is interfaced to FPGA.
this file is main file in which vga timing is maintained.
- 2023-07-29 01:40:03下载
- 积分：1
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VHDL_freerisc8
说明： 一个8位RiSC单片机的VHDL代码，
具有很好的参考价值。(an eight RiSC SCM VHDL code, is a good reference value.)
- 2006-02-15 10:58:14下载
- 积分：1
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fpalign_struct
floating point alignment
- 2013-03-11 16:53:31下载
- 积分：1
