-
master and slave code
集成电路的规模日益扩大
- 2022-03-02 13:07:25下载
- 积分：1
-
Decodificador
System Verilog decodificator.
Enters a value(binary), drops hundreds, tens and units in BCD
- 2013-05-15 02:11:45下载
- 积分：1
-
3P3_wimdow
图像插值算法，窗口为3*3,用于图像的除去死点，以及提高清晰度或者使图像柔和(3*3 window)
- 2012-02-28 15:36:02下载
- 积分：1
-
ix746
Nonlinear discrete system identification, It uses a pulse of consumer law, Partial least squares method.
- 2017-08-28 20:46:28下载
- 积分：1
-
北大verilog课件，数字集成电路设计入门，从HDL到版图
北大verilog课件，数字集成电路设计入门，从HDL到版图-North Verilog courseware, digital IC design entry, from HDL to the map
- 2022-07-24 16:14:44下载
- 积分：1
-
RD1006
RD1006--I2C与存储器的IP
代码及说明文档，lattice提供，I2C Controller for Serial EEPROMs 源代码可用，并且包含tb文件-RD1006-- I2C and memory IP code and documentation. Lattice offer I2C Controller for Serial EEPROMs source code available, and document contains tb-
- 2023-07-29 23:55:03下载
- 积分：1
-
一个FPGA的AVR_Core
仅供测试~
一个FPGA的AVR_Core
仅供测试~-AVR_Core an FPGA-only test ~
- 2023-08-16 08:25:03下载
- 积分：1
-
exercise3
用verilog实现dsp与Fpga接口的同步设计，其功能包括读写操作及四个功能模块，采用两个fifo实现不同时钟域的地址与数据的转换，在quartus ii11.0环境下运行，运行此程序之前需运行将调用fifo。(Dsp using verilog achieve synchronization with Fpga interface design, its features include read and write operations and four functional modules, using two different clock domains to achieve fifo address and data conversion in quartus ii11.0 environment to run, run this program required before running calls fifo.)
- 2013-08-30 11:12:09下载
- 积分：1
-
双向移位寄存器的VHDL源程序,自己做实验编写的可以用 谢谢大家...
双向移位寄存器的VHDL源程序,自己做实验编写的可以用 谢谢大家-Bi-directional shift register of the VHDL source code, prepared by their own experiments can be used Thank you
- 2022-02-11 10:52:42下载
- 积分：1
-
FSK
2FSK的matlab仿真，叠加了高斯白噪声(2FSK matlab simulation, superimposed on a Gaussian white noise)
- 2021-04-13 02:58:56下载
- 积分：1
