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看了好多网了，发现有2to4译码，3to8译码，今天我要用4to16译码，写完了就发了上来...
看了好多网了，发现有2to4译码，3to8译码，今天我要用4to16译码，写完了就发了上来-saw a lot of net and found 2to4 decoding, 3to8 decoding, today, I must 4to16 decoding, finished on the fat in the ranks
- 2022-03-09 18:15:27下载
- 积分：1
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Hardware-CNN-master
说明： Convolutional neural network code for fpga
- 2019-02-27 15:21:22下载
- 积分：1
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sender的verilog
利用fpga实现
sender的verilog
利用fpga实现-sender using the Verilog FPGA realize
- 2022-05-26 20:43:04下载
- 积分：1
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ep2c5 实现 段寄存器,实验一
verilog语言，quartus 2 仿真
ep2c5 实现 段寄存器,实验一
verilog语言，quartus 2 仿真-Register ep2c5 achieve above experiment a verilog language, quartus 2 Simulation
- 2022-03-19 07:48:20下载
- 积分：1
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tlc549
数字电压表的实现，VHDL语言实现，AD采用TLC549，通过学习，了解AD采集过程(The realization of digital voltage meter, VHDL language, AD using TLC549, by learning to understand the acquisition process AD)
- 2009-07-09 09:15:15下载
- 积分：1
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ahb_interface
AHB BUS, Master Slave Arbiter -- example(AHB BUS, Master Slave Arbiter)
- 2020-11-23 10:39:35下载
- 积分：1
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CD1_MT9V034_RAW_TRANS
基于FPGA的UDP网络图像传输实验，FPGA完成了MT9V034的RAW图像采集缓存，NIOS完成了图像的UDP封包，DM9000芯片完成了MAC和PHY的功能。(Based on the UDP FPGA network image transmission experiment, FPGA completed the RAW MT9V034 image acquisition cache, NIOS completed the image of the UDP packets, DM9000 chip MAC and PHY completed the function.)
- 2016-07-13 10:11:46下载
- 积分：1
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Verilog&Vhdl混语言对SDRAM的控制源代码，提供了很好的例子，顶层文件为sdrm.v！...
Verilog&Vhdl混语言对SDRAM的控制源代码，提供了很好的例子，顶层文件为sdrm.v！-VerilogVhdl mixed language SDRAM control of the source code, provided a good example of top-level documents sdrm.v!
- 2022-03-18 22:36:54下载
- 积分：1
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C-V2X-master
LTE is an abbreviation for Long Term Evolution.
- 2019-06-29 01:08:09下载
- 积分：1
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clock_gyc_system
基于用户自定义模块的实时时钟的设计；Qsys硬件设计；(Custom real-time clock module-based design Qsys hardware design )
- 2020-12-23 09:19:08下载
- 积分：1
