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LFM
该程序使用Verilog语言产生LFM信号(The program uses Verilog language to generate LFM signals.)
- 2021-04-19 09:38:51下载
- 积分：1
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主要是通过Altera公司的Cuclone系列的FPGA
主要是通过Altera公司的Cuclone系列的FPGA-EP1C3T144C8产生余弦波的源代码 基于LPM-ROM余弦波一周期含有256个10位数据；-Mainly through Altera s Cuclone series of FPGA-EP1C3T144C8 cosine wave generated source code based on the LPM-ROM cosine wave of one cycle containing 256 10-bit data
- 2023-06-17 01:00:03下载
- 积分：1
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利用扫描加记数程序实现百进制,适合VHDL的初学者使用.
利用扫描加记数程序实现百进制,适合VHDL的初学者使用.-increase in the use of scanning program in mind several hundred 229 and is suitable for beginners to use VHDL.
- 2022-03-21 06:59:03下载
- 积分：1
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32FIRVHDL
基于FPGA的32阶FIR数字滤波器设计 源程序。设计使用了并行乘法器，运行速度更快，占用内存更小，延迟更小。
(32 order FIR digital filter based on FPGA design source program. Design USES parallel multiplier, faster and less memory, less delay.)
- 2014-05-12 21:11:19下载
- 积分：1
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truck_lights
Lights, Car light emulator for turn, stop and emergency
- 2012-11-06 18:27:06下载
- 积分：1
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mul
实现有限域中乘法，输入二个普通二级制数，输出在本原多项式的乘法结果(Achieve limited multiplication field, enter the number of two-tier system of two ordinary output in primitive polynomial multiplication results)
- 2014-01-12 22:52:38下载
- 积分：1
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Frame-synchronizer-
原创，帧同步器的Verilog代码，在FPGA上验证实现过，无误。作为通信系统帧传输的仿真，有限状态机同步态和失步态的切换仿真。(Original Verilog code for frame synchronization, verify the implementation on the FPGA, and correct. Frame transmission as the communication system simulation, finite state machine synchronous state and the loss of the switching simulation of gait.)
- 2012-04-01 19:38:54下载
- 积分：1
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FPGA_SPWM
此代码是由FPGA产生SPWM波的代码，简单易懂(use FPGA to generate SPWM)
- 2019-02-19 16:12:33下载
- 积分：1
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done, would not have introduced the document on the bar, IEEE1364 standard (open...
做EDA的，就不用介绍这个文件了吧，IEEE1364标准（开放）。-done, would not have introduced the document on the bar, IEEE1364 standard (open).
- 2022-03-25 09:59:57下载
- 积分：1
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verilog-ethernet
说明： Collection of Ethernet-related components for gigabit, 10G, and 25G packet processing (8 bit and 64 bit datapaths). Includes modules for handling Ethernet frames as well as IP, UDP, and ARP and the components for constructing a complete UDP/IP stack. Includes MAC modules for gigabit and 10G/25G, a 10G/25G PCS/PMA PHY module, and a 10G/25G combination MAC/PCS/PMA module. Includes various PTP related components for implementing systems that require precise time synchronization. Also includes full MyHDL testbench with intelligent bus cosimulation endpoints.
- 2021-04-17 23:38:52下载
- 积分：1
