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DPD_project
预失真算法中，包络解波部分的verilog代码，有部分错误(envelope calculation of DPD algorithm ，verilong HDL language)
- 2014-04-26 15:45:21下载
- 积分：1
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OFDM-analysis-and-simulation
实现了光OFDM模块的各个功能，同时仿真分析了OFDM的载波幅度谱、相位谱、每个载波对应的时域信号、整个时域/频域的OFDM、每个接收符号的分布图。计算了相位差等等(To achieve the various functions of the optical OFDM module, the simulation analysis of the the the OFDM carrier amplitude spectrum and phase spectrum, and the time domain signal corresponding to each carrier, the whole time domain/frequency domain OFDM, each reception symbol maps. Calculated phase difference)
- 2020-10-17 16:17:28下载
- 积分：1
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formal_verification
说明： 现在最流行的RTL设计方法之一，本书为全球流行的设计入门书籍(One of the most popular RTL design methods nowadays, this book is an introductory book for popular design all over the world.)
- 2020-06-23 22:00:02下载
- 积分：1
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Common examples of VHDL, suitable for beginners, there are examples of commonly...
VHDL常用实例，适合初学者，有计时器等常用例子-Common examples of VHDL, suitable for beginners, there are examples of commonly used timer, etc.
- 2023-07-12 06:25:03下载
- 积分：1
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SPI
design and implement a digital system on the Altera NIOS board which will read an analogue input using MicroChip’s SPI MCP3202 12-Bit A/D converter. The 8 most significant bits of the converted data will be displayed on two seven segments of the NIOS development board. The sampling frequency is 20kHZ. Use a potentiometer.(design and implement a digital system on the Altera NIOS board which will read an analogue input using MicroChip' s SPI MCP3202 12-Bit A/D converter. The 8 most significant bits of the converted data will be displayed on two seven segments of the NIOS development board . The sampling frequency is 20kHZ. Use a potentiometer.)
- 2010-08-17 19:16:12下载
- 积分：1
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eluosi_game
使用Quartus II 9.1完成俄罗斯方块游戏，只要使用有VGA和键盘接口的FPGA开发板就行实现。操作简单，使用的是VHDL和Verilog语言(Use the Quartus II 9.1 to complete the tetris game, as long as you use a VGA and keyboard interface implementation of FPGA development board. The operation is simple, the use of VHDL and the Verilog language)
- 2020-11-06 12:49:49下载
- 积分：1
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buffer
用verilog实现的buffer，经过了fpga平台验证。(Implement buffer with verilog.)
- 2020-10-28 12:19:58下载
- 积分：1
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WorkSpace
计算三平动并联机构工作空间，自己编的，测试可以用(Calculation of three translation parallel mechanism)
- 2021-04-17 18:08:52下载
- 积分：1
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nios2_led_one
使用nios2点亮一个led灯，使用软件quartus13.0，开发板de2-115(nios2 led quartus13.0 de2-115)
- 2013-12-11 14:32:16下载
- 积分：1
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Lab1_flash_led
EGO_1流水灯显示代码步骤过程全都有适合初学者练手(EGO_1 nxoiaocijpwjcpoewopvkpowevko)
- 2020-12-22 11:39:08下载
- 积分：1
