登录
首页 » VHDL » A VEILOG HDL procedures, can be applied directly,

A VEILOG HDL procedures, can be applied directly,

于 2023-02-01 发布 文件大小:101.87 kB
0 132
下载积分: 2 下载次数: 1

代码说明:

一个VEILOG HDL程序,可以直接应用,-A VEILOG HDL procedures, can be applied directly,

下载说明:请别用迅雷下载,失败请重下,重下不扣分!

发表评论

0 个回复

  • 基于FPGA的数字频率计设计
    使用飓风开发板,完成了100M,频率计设计,并可在数码管显示
    2022-02-25 11:23:58下载
    积分:1
  • adder8
    8位加法器源代码,vivado实现编写。(8 adder Source, vivado achieve write.)
    2015-12-01 20:35:55下载
    积分:1
  • FPGA
    FPGA项目开发实战讲解 [李宪强编著][电子工业出版社][2015.04][248页].pdf(FPGA Project Development combat explain [Li Xingjiang ed] [Electronic Industry Press] [2015.04] [248] .pdf)
    2016-07-13 08:53:07下载
    积分:1
  • 8位十六进制频率计设计 根据频率的定义和频率测量的基本原理,测定信号的频率必须有一个脉宽为1s的输入信号脉冲计数允许信号;1s计数结束后,计数值被锁入锁存器,计...
    8位十六进制频率计设计 根据频率的定义和频率测量的基本原理,测定信号的频率必须有一个脉宽为1s的输入信号脉冲计数允许信号;1s计数结束后,计数值被锁入锁存器,计数器清零,为下一测频计数周期做好准备。测频控制信号可由一个独立的发生器(FTCTRL)来产生。-8-bit hexadecimal Cymometer designed in accordance with the definition of frequency and frequency of the basic principles of measurement to determine the frequency of the signal must have a pulse width of the input signal for 1s permit pulse counting signal 1s counting after the total value was locked into the lock depositors, counters cleared for the next count cycle frequency measurement ready. Frequency control signal generator may be an independent (FTCTRL) to generate.
    2022-06-19 17:20:21下载
    积分:1
  • time_frequency_analysis
    一种合并频率的方法对时频分析及其有用所以才上传(a fast combination)
    2013-12-04 10:13:24下载
    积分:1
  • GPS
    在fpga中对GPS信息采集程序。具有很好的参考性(In the fpga in the GPS information collection procedures. Has a very good reference)
    2011-11-17 13:49:20下载
    积分:1
  • 2022-05-01 00:03:25下载
    积分:1
  • help_lib
    1.JESD204B协议 2.Xilinx的JESD204B phy 核手册 3.Xilinx的JESD204B rx_tx 核手册7.1 4.Xilinx的JESD204B rx_tx 核手册7.2 5.verilog实现串口发送(1.JESD204B protocol 2.Xilinx JESD204B PHY core manual 3.Xilinx JESD204B rx_tx core manual 7.1 4.Xilinx JESD204B rx_tx core manual 7.2 5.verilog to achieve serial transmission)
    2017-11-15 16:09:22下载
    积分:1
  • ram
    代码实现了一个由32位寄存器组成的寄存器组,并有多个控制输入和两个输出,方便使用。(The code implements a 32-bit register consisting of registers, and there are multiple control inputs and two outputs, easy to use.)
    2009-10-23 16:09:44下载
    积分:1
  • CCMU
    代码是一个复数乘法器,两个复数相乘,只用到了2个实数相乘,运算量少(Code is a complex multiplier, two complex multiplication, uses only real number multiplied by 2, operations less)
    2011-11-04 11:56:47下载
    积分:1
  • 696518资源总数
  • 105895会员总数
  • 18今日下载