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俄罗斯方块
说明: 俄罗斯方块游戏,采用Verilog编写,整个工程文件,TFT/VGA显示(Tetris game, written by Verilog, the whole project file, TFT / VGA display)
- 2019-12-15 16:56:53下载
- 积分:1
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3input_xor
用Hspice实现一个三输入异或门,并分析其功耗和延时。(A three input XOR gate is implemented by Hspice, and its power consumption and delay are analyzed.)
- 2018-06-12 11:06:45下载
- 积分:1
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一个交通灯的vhdl语言实现 用 VC的 1.在指定的文件夹内查找某个文件 2.获取系统文件夹的路径, 要求显示windows system tem...
一个交通灯的vhdl语言实现 用 VC的 1.在指定的文件夹内查找某个文件 2.获取系统文件夹的路径, 要求显示windows system temp 当前目录的路径 C语言 跳马问题:在5*5的棋盘上,以编号为1的点出发,按日只跳马,要求不重复地跳所有位置,求出符合规则所有跳马的方案 1 6 15 10 21 14 9 20 5 16 19 2 7 22 11 8 13 24 17 4 25 18 3 12 23 -a traffic light VHDL language of a VC. The designated folders to search within a document 2. Access to the system folder path, requested that the current windows system temp directory path C language vault : 5* 5 in the chessboard to the No. 1 starting point, the only daily vault and asked not to repeat all locations to jump to get in line with all rules of the program vault 1 6 15 10 21 14 9 20 5 16 19 2 7 22 11 8 13 24 17 4 25 18 3 12 23
- 2022-02-14 11:48:06下载
- 积分:1
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入门,verilog语言,实现字符型液晶1602的显示,及按键控制
入门,verilog语言,实现字符型液晶1602的显示,及按键控制-verilog
- 2022-07-19 01:27:34下载
- 积分:1
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VHDL.Programming
这是这本书的第四个版本,现在这个版本不仅提供了VHDL语言的覆盖面,但设计方法的信息,以及。此版本将指导读者通过创建一个VHDL设计的过程中,模拟设计,综合设计,放置和布线设计,使用的重要模拟验证的最终结果,新的技术,称为全速调试,提供了极其快速设计验证。在这个版本的设计,例如已被更新(This is the fourth version of the book and this version now not only provides VHDL language coverage but design methodology information as well. This version will guide the reader through the process of creating a VHDL design, simulating the design, synthesizing the design, placing and routing the design, using VITAL simulation to verify the final result, and a new technique called At-Speed debugging that provides extremely fast design verification. The design example in this version has been updated to reflect.)
- 2012-04-08 19:36:36下载
- 积分:1
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基于fpga数字频率计的设计
数字频率计的设计,显示0~999的频率
整个程序代码都是通过vhdl语言来完善的
功能模块多样,详细的介绍了多模块的各个功能
- 2022-03-13 10:54:30下载
- 积分:1
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PLD与8051接口的参考设计 Xilinx提供的verilog源代码
PLD与8051接口的参考设计 Xilinx提供的verilog源代码-PLD 8051 interface with the Xilinx Reference Design for the Verilog source code
- 2022-05-12 14:58:28下载
- 积分:1
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跑马灯 简单实用很适合初学者 希望对大家有用
跑马灯 简单实用很适合初学者 希望对大家有用-Marquee is simple and practical very suitable for beginners want to be useful to everyone
- 2022-04-09 02:07:14下载
- 积分:1
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16QAM
QAM调制模块,可用于Quartus仿真与fpga硬件实现。(QAM Modulation Mode, can be used for Quartus simulation and FPGA.)
- 2013-12-27 10:01:48下载
- 积分:1
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f500
verilog coding for butterworth filter with cut off
frequency with 500hz
- 2014-02-19 15:37:09下载
- 积分:1