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RSA密码芯片的FPGA实现[1].part1.rar
RSA密码芯片的FPGA实现[1].part1.rar...
RSA密码芯片的FPGA实现[1].part1.rar
RSA密码芯片的FPGA实现[1].part1.rar-RSA password chip FPGA realization of [1]. Part1.rarRSA password chip FPGA realization of [1]. Part1.rar
- 2022-08-13 06:54:28下载
- 积分：1
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VGA的IP核，下载即可用，解压到指定目录下就可以了，参照里面的read me....
VGA的IP核，下载即可用，解压到指定目录下就可以了，参照里面的read me.-VGA
- 2022-02-02 20:02:28下载
- 积分：1
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i2c_master_top
i2c core : i2c master top
- 2012-05-23 01:17:22下载
- 积分：1
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timblogiw
timblogiw.c timberdale FPGA LogiWin Video In driver.
- 2015-04-21 10:34:21下载
- 积分：1
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verilog实现ALU的源代码，并提供了详细的测试平台！
verilog实现ALU的源代码，并提供了一个详细的测试平台！-achieve ALU Verilog source code, and provide a detailed test platform!
- 2022-03-15 13:01:46下载
- 积分：1
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vhdl_fir
在matlab仿真的基础上，用maxplus2实现等波纹法的程序代码(In matlab simulation, based on the use of such corrugated maxplus2 realize law code)
- 2008-05-21 20:30:35下载
- 积分：1
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uc1701x_SPI
UC1701串行编程例子，是一个很好的控制ＬＣＤ模块的Ｃ语言串行编程(UC1701 serial program)
- 2013-05-31 19:22:19下载
- 积分：1
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Synopsys-RTLSystemC
synopsys的systemc和RTl书籍清晰电子版，专业权威的EDA公司的培训资料(synopsys of systemc and RTl clear electronic version of books, professional authority of the EDA company' s training materials)
- 2010-08-11 11:49:49下载
- 积分：1
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widgets
CSS配合jquery制作完美漂亮的时钟，貌似在IE8下时钟不能获取时间啊！支持ie9、chrome、safari、firefox、opera （Chrome显示效果最佳，IE9下时钟无法工作）日历和骰子是原创，CSS3时钟并非原创但经过改良支持opera。数字日历的兼容性不错，圆形时钟就差点了，也希望一起交流，共同改进。(CSS with the jquery make perfect beautiful clock, seemingly in IE8 under the clock can not get the time ah! Support ie9, chrome, safari, firefox, opera (Chrome show the best results, the clock does not work under IE9) calendar and dice is original, CSS3 clock is not original but after improved support opera. Digital calendar compatibility is good, almost round the clock on, and also hope together, and work together to improve.)
- 2014-10-31 09:25:37下载
- 积分：1
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SimpleVOut-master
SimpleVOut (SVO) is a simple set of FPGA cores for creating video signals
in various formats. The cores connect using AXI-streams. Most configurations
(resolution, framerate, colordepth, etc.) are set at compile-time using
Verilog parameters. See svo_defines.vh for details on those parameters.
- 2020-06-24 21:20:01下载
- 积分：1
