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ModelSim Quick Start Guide, incidental text in an example of source code.
modelsim快速入门教程，附带文中范例源代码。-ModelSim Quick Start Guide, incidental text in an example of source code.
- 2023-05-02 04:50:04下载
- 积分：1
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Continuous_acoustic_emission_board
说明： 多通道连续声发射数据采集，每个通道最大5M，采用verilog编程，内部用状态机。(Multichannel continuous acoustic emission data acquisition, each channel up to 5M, using Verilog programming, internal state machine.)
- 2020-06-25 13:00:01下载
- 积分：1
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c51
51数字钟带各种扩展年，月，日等并且可预置。用汇编语言写的(51 digital clock with extended assembly language)
- 2012-11-09 08:41:02下载
- 积分：1
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电梯
利用verilog编写的电梯程序，实现基本的电梯运行功能(Elevator program written by Verilog)
- 2018-11-25 11:39:50下载
- 积分：1
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FPGASPI
FPGA SPI 主要模块全部涵盖 时序解释 与DSP通信(FPGA SPI Timing interpretation covering all main modules communicate with the DSP)
- 2020-12-09 13:49:20下载
- 积分：1
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This is a realization of I2C interface VHDL module, I2C protocol to achieve
这是一个I2C接口的VHDL实现模块，实现I2C协议-This is a realization of I2C interface VHDL module, I2C protocol to achieve
- 2023-08-26 08:25:03下载
- 积分：1
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Multi_function
01 线性调频信号的卷积功能测试（匹配）
02 LFM一维距离像
03 MATLAB联合FPGA仿真输入/输出功能测试
04 解速度模糊
05 扩展目标检测(01 LFM Test function of "conv"
02 LFM Range
03 MATLAB and FPGA
04 resovle speed resolution
05 Extended moving target)
- 2013-05-03 15:53:43下载
- 积分：1
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Xcell1
W elcome to X CELL, the new
Xilinx customer newsletter.
By sending us your development
system registration card you automatically
became n charter subscriber
to this quarterly publication. It is our
intent to make this an informative,
easy to read, responsive and-hopefully-
interactive newsletter. We
want to supply you with early and
correct information, tell you about
the status of our products and about
our plans, about bugs and their workarounds,
give you applications ideas
and convey to you some of the en thusiasm
that we feel for our Programmable
Gate Arrays.
If you have questions or suggestions,
please send them to me. II Letters
to the Editor make a newsletter
more lively.
Peter Alfke, Editor
- 2014-12-25 01:07:59下载
- 积分：1
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FPGASPI
FPGA SPI 主要模块全部涵盖 时序解释 与DSP通信(FPGA SPI Timing interpretation covering all main modules communicate with the DSP)
- 2020-12-09 13:49:20下载
- 积分：1
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vhdl,序列信号发生器，发出11101010，可更改为任意序列
vhdl,序列信号发生器，发出11101010，可更改为任意序列-vhdl, sequence signal generator, issued 11.10101 million, you can change an arbitrary sequence of
- 2023-08-12 03:05:03下载
- 积分：1
