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基于FPGA控制的DDS波形发生器
基于FPGA控制的DDS波形发生器,可在Cyclone IV系列板子上使用,已经过仿真验证(Based FPGA control DDS waveform generator in Cyclone IV series board on use, has been simulation)
- 2017-03-17 11:08:39下载
- 积分:1
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PipelineSim
一个计算机原理课程设计的作业,5级流水线CPU,指令集到代码均为自己设计,有最终报告文档,组建说明,并行除法,16位字长,定长指令,Verilog源代码,顶层设计图。结构简单,冲突解决方式也很简单,代码量小。(A computer theory course design work, five pipelined CPU, instruction set to the code are design, the final report documents the formation of parallel division, 16-bit word length, fixed-length instructions, Verilog source code, top level design. Simple structure, conflict resolution is also very simple, a small amount of code.)
- 2012-06-24 22:19:14下载
- 积分:1
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本代码介绍了使用VHDL开发FPGA的一般流程,最终采用了一种基于FPGA的数字频率的实现方法。该设计采用硬件描述语言VHDL,在软件开发平台ISE上完成,可以...
本代码介绍了使用VHDL开发FPGA的一般流程,最终采用了一种基于FPGA的数字频率的实现方法。该设计采用硬件描述语言VHDL,在软件开发平台ISE上完成,可以在较高速时钟频率(100MHz)下正常工作。该设计的频率计能准确的测量频率在1Hz到100MHz之间的信号。使用ModelSim仿真软件对VHDL程序做了仿真,并完成了综合布局布线,最终下载到芯片Spartan-II上取得良好测试效果。-the code on the FPGA using VHDL development of the general process, finally adopted a FPGA-based digital frequency method. The design using VHDL hardware description language, the software development platform ISE completed, the higher speed clock frequency (100MHz) under normal work. The design of the frequency meter can be accurately measured in a frequency of 100MHz between Hz signal. Use ModelSim VHDL simulation software to do the simulation process, and completed a comprehensive layout cabling, downloaded to the final chip Spartan-II made good on the test results.
- 2022-10-09 05:15:03下载
- 积分:1
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yangxiaoniu
杨小牛大神的软件无线电,做信道化或者宽带数字接收机的可以下载(Software Radio written by XiaoNiu Yang,people who deal with channelization or wideband digital receiver can download)
- 2016-08-26 16:20:21下载
- 积分:1
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用verilog HDL语言,通过一个4位移位寄存器实现一个信号转化为HDB3码并进行测试...
用verilog HDL语言,通过一个4位移位寄存器实现一个信号转化为HDB3码并进行测试
-Using verilog HDL language, through a 4-bit shift register realization of a signal into HDB3 code and test
- 2023-05-23 03:15:03下载
- 积分:1
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half_adrrrrder
FPGA上的一个半加器实例程序,通过测试,可以直接运行在fpga开发板上。(One and a half adder example on FPGA program, through the test, can be run directly on the FPGA development board)
- 2013-12-01 12:01:31下载
- 积分:1
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数码管显示
在FPGA EGO1的口袋平台上实现数码管滚动显示学号的功能(Rolling on the digital tube to display the school number)
- 2021-04-17 10:08:52下载
- 积分:1
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sync_bitops
Set a bit and return its old value.
- 2015-06-23 14:22:31下载
- 积分:1
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pc104接口的verilog代码,仅供参考
pc104接口的verilog代码,仅供参考-pc104 verilog interface code for reference purposes only
- 2022-12-27 10:00:03下载
- 积分:1
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它执行浮点运算单元
it performs the floating point arithmetic unit
- 2022-08-09 12:14:10下载
- 积分:1