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Classic_Manual_Verilog_programming_language
Verilog编程语言经典手册Classic Manual Verilog programming language(Verilog programming language classic manual Classic Manual Verilog programming language)
- 2010-07-30 09:31:49下载
- 积分:1
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VMD642_CPLD
本例程位于 VMD642_CPLD目录中。
使用 CPLD 实现辅助译码、LED 指示灯控制、看门狗等各种逻辑控制电路。源程序使
用 Verilog HDL书写,编译开发系统使用 Cypress公司的 Warp 6.3。(This routine is located VMD642_CPLD directory. Using CPLD implementation auxiliary decoding, LED indicator control, watchdog, and other logic control circuitry. Written using Verilog HDL source code, the compiler development system using Cypress' s Warp 6.3.)
- 2013-09-13 13:59:52下载
- 积分:1
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实例
FPGA 学习实例 动态时钟、面积、速度优化相关代码(Codes related to dynamic clock, area and speed optimization for learning examples of FPGA)
- 2020-06-22 22:40:02下载
- 积分:1
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用vlog语言编制程序CPU控制器源代码…
用vlog语言编写的cpu控制器源代码,用于fpga的硬件编程实验-vlog language used in the preparation of cpu controller source code for programming fpga hardware experiments
- 2022-02-15 12:37:59下载
- 积分:1
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xp2syscloclkpll
这个是讲pll的具体用法的,一般在fpga设计中都会用到 他,这个是lattice的xp2的pll的介绍,不过,fpga 都是相通的其他两家也差不多(Pll say this is the specific usage, the general design in the FPGA will use him, this is the lattice of the pll of xp2 introduction, however, fpga are connected to other two similar)
- 2007-10-31 21:03:07下载
- 积分:1
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8位乘法器的VHDL代码
资源描述该乘法器可用于过滤器,算术运算和;
- 2022-08-14 19:11:01下载
- 积分:1
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DDR2_16bit
说明: ddr2原理图设计,原厂电路图设计,很好很强大 16bit(ddr2 schematic design, the original schematic design, a very powerful 16bit)
- 2011-02-24 11:07:35下载
- 积分:1
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lisa-vhdl2va
通过modelsim仿真检测matlab生成滤波器效果。(Generate the filter through matlab and simulated by modelsim.)
- 2013-12-12 11:17:18下载
- 积分:1
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Arty-Z7-20-hdmi-out-master
说明: Arty Z7 20 HDMI output
- 2021-04-24 15:18:47下载
- 积分:1
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dazhuankuai
基于FPGA设计的经典打砖块小游戏。游戏简单易玩。(FPGA design based on the classic Arkanoid game. Game easy to play.)
- 2013-11-26 09:40:37下载
- 积分:1