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MIPS
Top level Architecture of MIPS Processor
- 2009-08-17 21:08:17下载
- 积分：1
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很好的quartus软件仿真教程，flash版。
很好的quartus软件仿真教程，flash版。-Good quartus software simulation tutorials, flash version.
- 2023-03-08 19:40:06下载
- 积分：1
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使用正弦波Modelsim仿真生成程序
用modelsim仿真一个正弦波产生程序-modelsim simulation using a sine wave generated procedures
- 2022-08-20 03:57:11下载
- 积分：1
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VHDL
EDA技术以EDA软件工具为开发环境，以可编程逻辑器件为实验载体，实现源代码编程和仿真功能。VHDL作为一种标准化的硬件描述语言用于描述数字系统的结构、行为、功能和接口。本设计提出了一种基于VHDL语言的编码器和译码器的实现方法。编码器与译码器是计算机电路中基本的器件，本课程设计采用EDA技术设计编码和译码器。编码器由8线-3线优先编码器作为实例代表，译码器则包含3线-8线译码器和2线-4线译码器两个实例模块组成。课程设计采用硬件描述语言VHDL把电路按模块化方式进行设计，然后进行编程、时序仿真和分析等。课程设计结构简单，使用方便，具有一定的应用价值。
(EDA technology take the EDA software as tools for the development of the environment,programmable logic devices in experimental carrier,the realiztion of the source code programming and simulation. The VHDL as a standardized hardware description language used to describe the struction of digital systems,behavior,function and interface. The paper proposes a method for encoder and decoder based on the VHDL language.Encoder and decoder is a basic computer circuit devices.This Curriculum design by EDA design encoder and decoder.Encoders from 8- 3 priority encoder for example,and decoder includes 3- 8 decoder and the 2- 4 examples of the two decoder modules.And then to program, the timing simulation and analysis.Curriculum design, simple structure, easy to use and has a value.)
- 2011-06-22 21:23:30下载
- 积分：1
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VHDL实现SPI功能源代码
VHDL实现SPI功能源代码
-- The SPI bus is a 3 wire bus that in effect links a serial shift
-- register between the "master" and the "slave". Typically both the
-- master and slave have an 8 bit shift register so the combined
-- register is 16 bits. When an SPI transfer takes place, the master and
-- slave shift their shift registers 8 bits and thus exchange their 8
-- bit register values.-SPI realize the functional VHDL source code The SPI bus is a 3 wire bus that in effect links a serial shift register between the
- 2022-01-26 00:50:40下载
- 积分：1
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add16
designing of 16 bit adder using 4 bit adder using verilog code
- 2012-09-10 14:40:32下载
- 积分：1
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Quartus II TimeQuest时序分析器说明书
说明： Quartus II TimeQuest 时序分析器说明书；这本手册包含一组设计场景、约束指南以及相关建议。您应该熟悉 TimeQuest Timing Analyzer 和 Synopsys Design Constraint(SDC) 的基础知识，以便正确地使用这些指南。(Quartus II timequest timing analyzer manual; this manual contains a set of design scenarios, constraint guidelines, and related recommendations. You should be familiar with the basics of timequest timing analyzer and Synopsys design constraint (SDC) to use these guidelines correctly.)
- 2020-08-07 17:48:31下载
- 积分：1
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SPI接口VHDL代码,内有说明,很详细.
SPI接口VHDL代码,内有说明,很详细.-SPI interface VHDL code, which has made it clear that, in great detail.
- 2022-03-31 21:18:26下载
- 积分：1
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Xilinx公司网站下的SDRAM Controller的参考设计，经过验证
Xilinx公司网站下的SDRAM Controller的参考设计，经过验证-Xilinx website of SDRAM Controller reference design, validated
- 2022-04-11 09:06:46下载
- 积分：1
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simpleCpu
relative cpu design implementation
- 2013-08-14 21:22:39下载
- 积分：1
