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VHDL-100-examples
VHDL 的100例程代码,能够使你熟练掌握VHDL语言的编写(100 routines of VHDL code, enabling you to master the preparation of the VHDL language)
- 2012-07-31 11:17:51下载
- 积分:1
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sim
csapp 第二版 体系结构实验 答案 第三个部分能跑58分(the second edition csapp architecture experiment the third part of the answer can run 58 minutes)
- 2013-05-20 10:28:00下载
- 积分:1
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eDP
eDP接口TFT-LCD显示驱动原码(verilog+c)(eDP Interface TFT-LCD display driver source code (verilog+c))
- 2020-10-17 09:17:27下载
- 积分:1
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GPU_Programming_Guide_Chinese
GPU编程的经典之作,值得一读。 GPU运算效率比CPU高出一截,学习GPU编程会大有裨益(a book for GPU_Programming)
- 2012-10-19 16:32:00下载
- 积分:1
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Dcache设计
设计了一款Dcache,两路组相联,使用了LRU的替换算法。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。。
- 2022-05-05 17:44:29下载
- 积分:1
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verilog实现有限域GF(28)弱对偶基乘法器
采用verilog实现的有限域GF(28)弱对偶基乘法器,本原多项式: p(x) = x^8 + x^4 + x^3 + x^2 + 1 ,多项式基: {1, a^1, a^2, a^3, a^4, a^5, a^6, a^7},弱对偶基: {1+a^2, a^1, 1, a^7, a^6, a^5, a^4, a^3+a^7}
- 2022-07-03 03:48:26下载
- 积分:1
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my
说明: 64位数据的CRC-32校验的,Verilog实现,算法并行优化(64-bit data CRC-32 checksum, Verilog implementation of a parallel optimization algorithm)
- 2011-09-17 19:36:16下载
- 积分:1
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complex_timing_by_Primetime
用PrimeTime的技巧,解决复杂时钟问题。(The world of telecommunications chips is full of messy clocking situations. This paper will cover the tricks and tehniques that author Paul Zimmer has developed to avoid the need to pour over reams of timing reports looking for problems. Best paper winner at SNUG San Jose 2001!)
- 2012-08-05 19:07:47下载
- 积分:1
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Vhdl_testbench
vhdl 的testbench编写教程,英文ppt以及源码工程(Write tutorials, as well as English ppt Source of engineering vhdl testbench)
- 2016-08-29 10:09:05下载
- 积分:1
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24小时计时时钟
说明: 实现24小时计时,因为位数不够,这里是12进位,可自行调整进位数(Realize 24-hour timing, because the number of digits is not enough, here is 12 carry, you can adjust the carry number by yourself.)
- 2020-06-23 19:40:01下载
- 积分:1