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ad0809
对ad0809的控制代码( ad0809control)
- 2010-08-28 15:00:50下载
- 积分：1
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getCPU
获取主机CPU信息，VS2008编译通过，含详细说明(Get information on the host CPU, VS2008 compiler, containing detailed instructions)
- 2014-11-27 10:07:21下载
- 积分：1
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fpga_video_game-master
在开发板EGO1上实现的直升机飞行游戏，随时间的累积，速度不断加快，数码管显示积分( Helicopter game in verilog)
- 2021-05-07 07:58:37下载
- 积分：1
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frame_decode_and_encode
一个用Verilog编写的编帧、解帧及码速匹配的程序，相当经典(Verilog prepared with a series of frames, frames and solutions yards speed matching procedures, rather classic!)
- 2006-07-12 15:10:07下载
- 积分：1
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eda
EDA 正弦信号发生器：正弦信号发生器的结构有四部分组成，如图1所示。20MHZ经锁相环PLL20输出一路倍频的32MHZ片内时钟,16位计数器或分频器CNT6，6位计数器或地址发生器CN6，正弦波数据存储器data_rom。另外还需D/A0832（图中未画出）将数字信号转化为模拟信号。此设计中利用锁相环PLL20输入频率为20MHZ的时钟，输出一路分频的频率为32MHZ的片内时钟，与直接来自外部的时钟相比，这种片内时钟可以减少时钟延时和时钟变形，以减少片外干扰 还可以改善时钟的建立时间和保持时间，是系统稳定工作的保证。CNT6用来将32MHZ进行8分频得到4096HZ的频率提供给CN6与data_rom时钟信号。由CLK端输入20MHZ的时钟信号，在DOUT端就可输出稳定的正弦信号。(Sine signal generator has the structure of four parts, as shown in figure 1 below. The 20 MHZ phase lock loop PLL20 output all the way of frequency doubled within 32 MHZ slice clock, 16 counter or prescaler CNT6, six counter or address generator CN6, sine data storage data_rom. In addition to D/A0832 (shown in not draw) will digital signal into analog signals. This design using the phase lock loop PLL20 input frequency for 20 MHZ clock, the output of the frequency of all points frequency of 32 pieces (MHZ clock, and comes directly from the external clock, compared to this piece of clock can reduce the clock in delay and clock deformation, to reduce the interference of Can also improve the establishment of the clock time and keep time, is the system stability of assurance. CNT6 used to will and to 8 MHZ get 4096 HZ dividing the frequency to provide CN6 and data_rom clock signal. The input by CLK 20 MHZ clock signal, in DOUT end can output stable sine signals.
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- 2021-03-07 15:49:29下载
- 积分：1
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Buffer-DAQ
基于研华采集卡的FIFO双缓存区高速数据采集(FIFO DAQ)
- 2015-01-11 19:09:49下载
- 积分：1
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rs_204_188----v1.0
RS 编码和解码Verilog Code, 实现了RS（204,188)的编码和译码；(RS Coding and Decoding Verilog code， implement RS（204,188) )
- 2021-03-25 20:29:14下载
- 积分：1
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module_dem
用verilog编写的信号调制解调程序，包括ask,fsk,qpsk的fpga实现(Prepared using verilog signal modulation and demodulation process, including ask, fsk, qpsk of fpga implementation)
- 2009-10-14 14:47:30下载
- 积分：1
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RS232_VHDL
FPGA控制RS232来实现串口通信，非常好的串口程序。(FPGA control RS232 serial communication to achieve very good serial procedures.)
- 2020-12-28 14:49:01下载
- 积分：1
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UML_2_Pour_les_bases_de_donnees
UML2 apprendre a modeliser a l aide de UML
- 2014-02-25 01:32:23下载
- 积分：1
