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PR-QMF
实现基于matlab的QMFB的完全重建,是一篇经过仿真且经过测试的正确的代码,可用价值比较高。(Based on matlab QMFB the completely rebuilt, is a through simulation and tested the correct code, can be relatively high value.)
- 2012-12-14 11:49:30下载
- 积分:1
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使用vhdl语言编写的100个常用程序的例子
使用vhdl语言编写的100个常用程序的例子-The use of VHDL language 100 examples of commonly used procedures
- 2022-08-18 05:39:29下载
- 积分:1
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CameraLink_Oserdes2_test
40M时钟输入经过iserdes倍频到960M(input 40M o clock and output 960M )
- 2014-02-25 14:06:38下载
- 积分:1
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PID
说明: 利用Verilog语言实现PID增量式控制,输出占空比(Using Verilog language to realize PID incremental control and output duty cycle)
- 2020-04-24 10:06:59下载
- 积分:1
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91026977FC-protocal
光纤通道协议,包括FC-SW,FC-FS,FC-LS,FC-GS,FC-HBA,FC-AE-ASM等文档。
(Fibre Channel protocols, including FC-SW, FC-FS, FC-LS, FC-GS, FC-HBA, FC-AE-ASM and other documents.)(Fiber channel protocol, including FC-SW, FC-FS, FC-LS, FC-GS, FC-HBA, FC-AE-ASM and other documents.
(Fibre Channel protocols, including FC-SW, FC-FS, FC-LS, FC-GS, FC-HBA, FC-AE-ASM and FC-AE-ASM))
- 2018-05-16 16:26:01下载
- 积分:1
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ADAPTIVEFILTER
采用vhdl代码描述自适应滤波器,具有很好的可参考性,和实用性(Vhdl code to describe the use of adaptive filter, can be found with a good nature and usefulness of)
- 2010-02-05 23:37:48下载
- 积分:1
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DDR3读写测试
MIG IP控制DDR3读写测试,于MIG IP核用户接口时序较复杂,这里给出扩展接口模块用于进一步简化接口时序。(MIG IP controls DDR3 reading and writing tests, and the time sequence of MIG IP kernel user interface is more complex.)
- 2018-03-28 16:01:36下载
- 积分:1
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完成PWM控制采用VHDL语言,你可以看看它。
done pwm control using vhdl ,you can look at it.
- 2022-02-06 06:14:03下载
- 积分:1
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timblogiw
timblogiw.c timberdale FPGA LogiWin Video In driver.
- 2015-04-21 10:34:21下载
- 积分:1
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dct_verilog
用FPGA实现dct变换。verilog语言实现,在quartus9.0中验证,含整个工程(dct transform verilog language in quartus9.0 verify, with the entire project)
- 2020-12-02 18:59:24下载
- 积分:1