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This program is Verlog language program, using QUARTUS6.0 preparation, program i...
本程序为Verlog语言程序，采用QUARTUS6.0编写，程序实现的功能是控制AD2S80的转换和和数据总线上数据的读取-This program is Verlog language program, using QUARTUS6.0 preparation, program implementation function is to control the conversion and AD2S80 and data bus to read data
- 2022-02-10 16:51:45下载
- 积分：1
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fffffff
如上图所示， Rst是低电平有效的系统复位信号，Clk是时钟信号。AB[5：0]是地址信号，DB[7：0]是数据信号，wr是低电平有效的写信号。start是启动信号。
模块中有一个64x8的双端口的存储器。系统复位结束后，可以通过AB、DB和wr信号向同步存储器写入数据。当写入64个数据后，给出一个Clk周期宽度的脉冲信号start，则系统从存储器0地址处开始读出数据，读出的8位数据从低位开始以3位为一组，每个时钟周期输出一组，即第一个时钟周期输出[2：0]位，第二个时钟周期输出[5：3]位，第三个周期输出1地址的[0]位和0地址的[7：6]位，直至将存储器中64x8数据全部输出。若最后一组不足三位，则高位补0。
(As shown above, Rst is an active-low system reset signal, Clk is a clock signal. AB [5: 0] is the address signal, DB [7: 0] is the data signal, wr write signal is active low. start is the start signal. Module in a dual port memory of 64x8. After the reset, you can write data to the synchronous memory by AB, DB and wr signals. When data is written to 64, given the width of a pulse signal Clk cycle start, the system begins to read the memory address 0, 8 data read out a low starting with three as a group, each clock outputs a set period, which is the first clock cycle of the output [2: 0] bits, the second clock cycle output [5: 3] position, the third cycle of the output of an address [0] and 0 address [7 : 6] bit, until all the data in memory 64x8 output. If the last group of less than three, the high 0s.)
- 2020-11-04 20:39:51下载
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Triscend supports the use of the Model Technology ModelSim logic simulator for V...
Triscend supports the use of the Model Technology ModelSim logic simulator for VHDL simulation of
designs implemented in the Configurable System Logic (CSL) portion of a Triscend device.
- 2023-07-10 18:40:02下载
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medianfilter
图像滤波中的中值滤波，有效滤除椒盐噪声，使用verilog语言编写(Image filtering in the median filter, effectively filter out salt and pepper noise, using verilog language)
- 2011-10-13 17:08:48下载
- 积分：1
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VHDL
软件式的VHDL学习工具，能帮助你更好的掌握VHDL的应用-VHDL-based software, learning tools, can help you better grasp the application of VHDL
- 2022-07-01 16:13:22下载
- 积分：1
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一个在CPLD，EPM70128上实现的PWM控制源程序。
一个在CPLD，EPM70128上实现的PWM控制源程序。-A CPLD, EPM70128 realize the PWM control on the source.
- 2022-05-08 12:21:41下载
- 积分：1
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Spartan6_GTP_PCIe_xfest_2009_v1_0
采用Xilinx公司的Spartan6 FPGA设计PCI Express的详细参考资料(Xilinx' s PCI Express, Spartan6 FPGA design, detailed reference information)
- 2012-08-30 10:01:33下载
- 积分：1
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硬件设计vhdl_cpu1，1。您可以复制和分发该副本…
硬件设计vhdl_cpu1,1. You may copy and distribute verbatim copies of this core, as long -- as this file, and the other associated files, remain intact and -- unmodified. Modifications are outlined below.-hardware design vhdl_cpu1, 1. You may copy and distribute verbatim copies of this core, as long-- as this file, and the other associated files, remain intact and-- unmodified. Modifications are outlined below.
- 2022-02-06 23:06:37下载
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LDPC.DIFFERENT-CODE-LONGTH
LDPC码不同码长对比。码率选择1/2.码长分别为256，512，1024.(LDPC codes of different code length contrast. Bitrate select 1/2 yards long were 256,512,1024.)
- 2012-11-22 10:53:04下载
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S02《Artix7修炼秘籍》MIG_DDR内存应用
说明： artix 7系列 fpga mig ddr3应用教程(Artix 7 Series FPGA MIG DDR3 Application Tutorial)
- 2020-03-22 12:58:39下载
- 积分：1
