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11_rs485_uart_top
说明: verilog编写的RS485读写驱动程序(RS485 read-write driver written by Verilog)
- 2020-03-08 12:28:10下载
- 积分:1
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FPGA-H265-Encoder
H.265的FPGA实现!!使用Verilog语言开发。(H.265 FPGA implementation! Developed using Verilog language.)
- 2021-03-08 19:49:28下载
- 积分:1
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Chebyshev-filter
利用matlab设计了一个切比雪夫滤波器,并且对滤波器性能进行了仿真分析。(Using the matlab design a chebyshev filter, and has carried on the simulation analysis on filter performance.
)
- 2013-09-05 20:04:36下载
- 积分:1
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multiplier
参数可配置的sequential 乘法器和booth 乘法器(verilog source code with configurable parameters for sequential multiplier and booth multiplier )
- 2011-12-08 15:14:04下载
- 积分:1
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hgb_pci_host
说明: 内有一PCI 主 和PCI从,PCI TARGET 都是公开代码的,是工程文件,有仿真工程,使用说明。觉得好的就推荐一下。
本PCI_HOST目前支持:
1、 对目标PCI_T进行配置;
2、 对目标进行单周期读写;
3、 可以工作在33MHZ和66MHZ
4、 支持目标跟不上时插入最长10时钟的等待。
ALTERA的PCI竟然收费的!!!软件里面调试仿真了半天,终于调通了,到了下载就突然弹出窗口说包含了有限制的IP CORE,是限制使用的(There is a PCI from PCI proprietors, PCI TARGET is open source, is the project document, there is simulation project, for use. Feel good about the recommendation. The PCI_HOST currently supports: 1, on the target configuration PCI_T 2, on the target for single-cycle read and write 3, can work in the 33Mhz and 66MHZ 4, to support the goals behind to insert a maximum of 10 clock hours of waiting. ALTERA the PCI even charges! ! ! Inside simulation software debugging for a long time, and finally had transferred to the download on the sudden pop-up window that contains a limited IP CORE, is to restrict the use of)
- 2008-09-16 18:57:25下载
- 积分:1
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fifoi
基于Xilinx Vertex2的可综合的2048x10位的读写可控制FIFO模块源代码,深度可控(Based on the Xilinx Vertex2 can be integrated 2048x10-bit read and write can control the FIFO module source code, the depth of controllable)
- 2008-12-19 00:17:51下载
- 积分:1
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100_Power_Tips_for_FPGA_Designersi
fpga高手设计实战真经100则,最新的FPGA英文书籍,值得参考学习(100 Power Tips for FPGA Designers,The new FPGA English books, worth learning)
- 2013-12-06 19:40:43下载
- 积分:1
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VGA256显示verilog程序
本程序是VGA256色方块显示的verilog HDL代码,包括XILINX系列virtex5 FPGA芯片的约束程序,用相应的板子连上VGA接口到显示屏上可以实现显示,显示分辨率1024×768,包括行场同步信号消隐程序、有效区域显示和256色VGA显示程序,代码安全可靠。
- 2022-05-20 16:37:03下载
- 积分:1
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fpga
FPGA代码,包含地址译码模块、16位锁存器、AD片选、死区及滤除窄脉冲、过流和短路保护、解除脉冲封锁模块、PWM模块、PWM选择
(FPGA code, including the address decoder module 16 latches, AD chip select, filter out the dead and narrow pulse, overcurrent and short circuit protection, lifting the blockade pulse module, PWM module, PWM selection)
- 2015-11-18 10:47:22下载
- 积分:1
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crc_verilog_xilinx
crc校验,非常好用,是从Xilinx的IP演化来的(crc脨 拢 脩茅 拢 卢 脟 鲁 拢 潞 脙脫脙 拢 卢 脢脟)
- 2021-03-01 11:49:34下载
- 积分:1