-
串行至并行转换器 UVM 代码
UVM 基于与教程有关的验证平台的体系结构中的所有组件的验证代码。最好的入手 UVM 的家伙
- 2022-07-10 05:49:00下载
- 积分：1
-
ControlUnit
Control Unit VHDL code. Xilinx Spartan 3E board
- 2012-03-15 13:29:40下载
- 积分：1
-
dcfifo_design_example
ALTERA发布的内部FIFO读写示例，很有参考价值，对初学者会有一定的帮助(ALTERA' s internal FIFO read and write examples of great reference value, there will be some help for beginners)
- 2010-11-13 23:31:11下载
- 积分：1
-
PWM
说明： 脉冲宽度调制，VHDL代码编写，包括QUARTUSII和MODELSIM工程以及testbench(Pulse width modulation, VHDL coding, including QUARTUSII and ModelSim engineering and Testbench)
- 2020-11-26 09:49:31下载
- 积分：1
-
ad9788_spi_ctrl
spi driver: Analog Device DAC ad9788 SPI Controller
- 2015-05-19 14:03:25下载
- 积分：1
-
HART-HT2015
HART 官方资料-HART协议采用基于Bell202标准的FSK频移键控信号，在低频的4-20mA模拟信号上叠加幅度为0.5mA的音频数字信号进行双向数字通讯，数据传输率为1.2kbps。(Official information-HART HART protocol based Bell202 standard frequency shift keying FSK signal at low frequencies 4-20mA analog signal amplitude is 0.5mA superimposed on the two-way audio digital signal digital communication, data transfer rate of 1.2kbps.)
- 2013-07-16 17:23:16下载
- 积分：1
-
Nut
UG二次开发，课程作业，研究生，学习，初学者，打孔，复杂体，阵列
UG C program，homework，student，study，first，hole，complex，many(
UG C program，homework，student，study，first，hole，complex，many)
- 2015-01-15 12:26:29下载
- 积分：1
-
hilbert_transformer.tar
hilbert 变换的vhdl源代码，来源于网上，本人也做过简单的8抽头的，但这个的算法还没搞懂，希望懂行的下载了研究一下，给个中文的简单的说明！(hilbert transform VHDL source code from the Internet, I have been a simple 8-tap, but even before they get to know this algorithm, I hope knowledgeable downloaded to look for a simple description of the Chinese!)
- 2020-10-19 21:37:25下载
- 积分：1
-
新建 Microsoft Word 文档
八位串行乘法器
缺点：乘法功能是正确的，但计算一次乘法需要8个周期，因此可以看出串行乘法器速度比较慢、时延大。
优点：该乘法器所占用的资源是所有类型乘法器中最少的，在低速的信号处理中有广泛的使用。(Eight bit serial multiplierDisadvantages: the multiplication function is correct, but the computation of one multiplication requires 8 cycles, so it can be seen that the serial multiplier is slow and time-consuming.
Advantages: the multiplier occupies the smallest number of resources in all types of multipliers, and is widely used in low speed signal processing.)
- 2018-06-10 21:19:29下载
- 积分：1
-
sobel
由Verilog编写在FPGA实现sobel算法应用于图像边缘检测，工程文件可在quartus13.1以上版本打开；工程使用到ram、fifo、pll三种ip核，design文件夹下包含ram、fifo、vga控制以及串口收发和sobel算法模块，sim和doc文件夹下分别包含modelsim的仿真模块和仿真结果；测试时将200*200分辨率的图片用matlab文件夹下的matlab脚本压缩、二值化，再将生成文件中数据用串口发给FPGA，边缘检测结果会通过VGA输出。(Written by Verilog in the FPGA implementation sobel algorithm applied to the edge detection of the image, the project file can be opened in the quartus13.1 or later project use ram, fifo, pll three ip kernel, design folder contains ram, fifo, vga control and Serial port transceiver and sobel algorithm module, sim and doc folder, respectively, include modelsim simulation module and simulation results test will be 200* 200 resolution picture matlab folder under the matlab script compression, binarization, and then generated Data in the file with the serial port to the FPGA, edge detection results will be output through the VGA.)
- 2021-01-15 21:08:46下载
- 积分：1
