-
VHDL language H.264 realize the opencore, meaning that documents, information su...
VHDL语言实现H.264的opencore，内涵说明文档、源码和文献等资料。 -VHDL language H.264 realize the opencore, meaning that documents, information such as source code and documentation.
- 2022-01-24 18:33:09下载
- 积分：1
-
MAC
this is a Multiplier and Accumulate (MAC). written in VHDL
- 2010-08-09 23:40:46下载
- 积分：1
-
Tcd1500c 时序代码
该代码主要是针对TCD1500c 的时序图，用verilog 语言实现的TCD1500c的时序图，利用modelsim 进行仿真，并且通过测试。
- 2022-09-12 11:05:02下载
- 积分：1
-
串uart的vhdl，verilog，lattic实现原码
里面有四个文件,分别UART 源码 (lattice version)uart 源码 (Veri...
串uart的vhdl，verilog，lattic实现原码
里面有四个文件,分别UART 源码 (lattice version)uart 源码 (Verilog)uart 源码 (VHDL)uart16550.tar-uart series of vhdl and verilog. lattic achieve the original code, there are four documents, Source respectively UART (lattice version) uart source (Verilog) uart source (VHDL) uart16550.tar
- 2022-04-12 23:45:53下载
- 积分：1
-
FPGA-powe-analysis-tool-EPE
FPGA功耗分析工具EPE用于分析FPGA系统的功耗(FPGA power analysis tools EPE is used to analyze the power consumption of the FPGA system)
- 2012-11-19 17:08:00下载
- 积分：1
-
VGA_DE2_6V
VGA显示彩条DE2_70开发板 验证过的(VGA display color bar DE2_70 development board validated)
- 2014-01-07 15:52:09下载
- 积分：1
-
yinpin_display0925
实现音频的I2S通信，音频柱的显示，及其噪声的处理等功能(Realization of audio I2S communications, audio column display, and its noise processing, and other functions)
- 2016-01-07 10:08:31下载
- 积分：1
-
通用：我新的FFT VHDL VHDL，我试图用Xilinx的FFT核，但当…
FFT vhdl generic: I m new to vhdl, and I tried to use xilinx fft core, but when I try to simulate it in test bench using ise simulator, I get zero results.
here is what I do:
1- from core generator I choose fft core and create .vhd & .vho & .xco files.
2- I add the .xco & .vhd files to my project.
3- I create a new vhdl source as a wrapper to the core and add the code from the .vho files where it exactly says, and take the ports of the component and add it to the entity of the wrapper file.-FFT vhdl generic: I m new to vhdl, and I tried to use xilinx fft core, but when I try to simulate it in test bench using ise simulator, I get zero results.
here is what I do:
1- from core generator I choose fft core and create .vhd & .vho & .xco files.
2- I add the .xco & .vhd files to my project.
3- I create a new vhdl source as a wrapper to the core and add the code from the .vho files where it exactly says, and take the ports of the component and add it to the entity o
- 2022-06-20 20:06:05下载
- 积分：1
-
With VHDL Design and Implementation of the multi
用vhdl设计实现的多功能电子钟，可有日历，闹钟，修改等多种功能-With VHDL Design and Implementation of the multi-functional electronic bell, can have a calendar, alarm clock, to amend a variety of functions such as
- 2022-03-11 03:55:41下载
- 积分：1
-
这是我自己写的4人表决器源码，在xilinx Spartan3E 上已经调试成功，拿出来与大家分享！...
这是我自己写的4人表决器源码，在xilinx Spartan3E 上已经调试成功，拿出来与大家分享！-that I wrote four voting machine source code, In xilinx Spartan3E debugging has been successful, with the show to share with you!
- 2022-01-27 20:17:47下载
- 积分：1
