-
imply logic
说明: 由忆阻器机制设计蕴含逻辑,内含testbench仿真文件(Design implied logic by memristor mechanism, including testbench simulation file)
- 2019-04-24 15:42:24下载
- 积分:1
-
frequency-agility
本程序为捷变频信号的verilog源代码设计实现的仿真,并含有相应捷变频信号在MATLAB仿真的结果(The procedure for the Czech Republic converted signal verilog source code design and implementation of the simulation, and the Czech Republic frequency signal containing the corresponding simulation results in MATLAB)
- 2015-10-15 10:37:54下载
- 积分:1
-
OQPSK
OPSK调制解调。代码思路很清晰,也很干净(Modulation demodulation OPSK. The code ideas very clear, and very clean)
- 2021-03-09 20:39:27下载
- 积分:1
-
ALTERA 的关于对SDRAM控制器操作的verilog相关程序,很不错绝对值得借鉴。...
ALTERA 的关于对SDRAM控制器操作的verilog相关程序,很不错绝对值得借鉴。-ALTERA on the operation of the SDRAM controller Verilog procedures, it is definitely worth a good draw.
- 2022-01-26 03:51:39下载
- 积分:1
-
基于FPGA的vga显示
实现基于FPGA的vga显示,亲测能编译得过,不同开发版应该要相应改动(PS: 不太了解)
- 2022-08-09 04:41:39下载
- 积分:1
-
VHDL-the-count
利用VHDL 硬件描述语言设计一个0~9999 的加法计数器。根据一定频率的触发
时钟,计数器进行加计数,并利用数码管进行显示,当计数到9999 时,从0 开始重新计数(Use of VHDL hardware description language design a 0 ~ 9999 addition counter. According to a certain frequency of the trigger
The clock, counter add count, and use digital pipes to show that when the count to 9999, starting from 0 to count
)
- 2012-01-13 14:01:38下载
- 积分:1
-
曼彻斯特编解码,是Verilog语言代码,不多介绍了,用途非常广泛了...
曼彻斯特编解码,是Verilog语言代码,不多介绍了,用途非常广泛了-Manchester encoding and decoding is the Verilog language code, introduced a few, a very extensive use
- 2022-04-01 23:58:18下载
- 积分:1
-
FPGA设计中的一些经典例子对学习FPGA的人会有帮助...
FPGA设计中的一些经典例子对学习FPGA的人会有帮助-FPGA design of some of the classic examples of people learning FPGA would be helpful
- 2022-05-23 13:59:58下载
- 积分:1
-
两个加法器和乘法器与并行处理的使用…
利用两个加法器和两个乘法器一起并行处理来实现
- 2022-05-28 05:02:29下载
- 积分:1
-
VHDL 的4*4键盘代码
VHDL 的4*4键盘代码-VHDL 4* 4 keyboard code
- 2023-04-05 11:35:04下载
- 积分:1